CS5560

18

DS713PP2

5/4/09

The following figure depicts the CS5560 device powered from a single 5V analog supply.

Figure 7. CS5560 Configured Using

AIN-

AIN+

SMODE

CS

RDY

CONV

BP/UP

MCLK

SLEEP

RST

TST

VREF-

VREF+

+4.096

Voltage

Reference

(NOTE 1)

+5 V

BUFEN

1. See Section 3.3 Voltage Reference for information on

required voltage reference performance criteria.

2. Locate capacitors so as to minimize loop length.

3. V1-, V2-, and VLR should be connected to the same

ground plane under the chip.

4. SCLK and SDO may require pull-down resistors in

some applications.

NOTES

0.1 µF

(V-) Buffers Off

(V+) Buffers On

0.1 µF

10 µF

V1+

V2+

V1-

V2-

VL

VLR

DCR

+5 V

+3.3 V to 1.8 V

0.1 µF

0.1 µF

X7R

0.1 µF

10

CS5560

49.9

47pF

4.99k

4700pF

C0G

49.9

47pF

4.99k

4700pF

C0G

+0.452 V

4.548 V

2.5 V

+4.548 V

+0.452 V

2.5 V

2.048 V

4.096 V

VLR2

50