8560EC

8561EC

8562EC

8563EC

8564EC, 8565EC

100 MHz to 2 GHz

0.7/0.7/–/–

0.9/0.8/–/–

1.0/0.8/–/–

0.9/0.8/–/–

30 Hz 1 to 2.9 GHz

1/0.8/1.5/1.0

1.0/0.7/1.75/1.0

1.25/0.8/1.8/1.0

1.25/0.8/1.8/1.0

1.0/0.8/1.5/1.0

2.9 GHz to 6.46.GHz

1.5/1.1/2.5/1.5

1.5/1.1/2.5/1.5

1.5/1.0/2.4/1.5

1.7/1.4/2.6/1.8

6.46 to 13.2 GHz

2.2/1.5/2.9/2.0

2.2/1.5/2.9/2.0

2.6/2.2/3.0/2.8

13.2 to 22 GHz

2.5/1.5/4.0/2.5

2.5/2.5/4.0/3.5

22 to 26.8 GHz

3.3/2.2/4.0/2.5

3.3/2.2/4.5/4.0

26.8 to 31.15 GHz

3.1/2.9/4.0/3.0

31.15 GHz to 40 GHz (Agilent 8564EC)

2.6/2.4/4.0/3.2

31.15 GHz to 50 GHz (Agilent 8565EC)

3.2/3.0/4.0/4.0

Band switching uncertainty

±1 dB (added to relative frequency response for between-band measurements)

Calibrator output

Input attenuator

Switching uncertainty (referenced to 10 dB attenuation)

30 Hz to 2.9 GHz for 20 to 70 dB settings of input attenuator:

±0.6 dB/10 dB step, 1.8 dB maximum

Repeatability ±0.1 dB (nominal)

IF gain uncertainty

±1 dB (0 to –80 dBm reference levels with 10 dB input attenuation)

IF alignment uncertainty

±0.5 dB (additional uncertainty only when using 300 Hz RBW)

Resolution bandwidth switching uncertainty

±0.5 dB (relative to 300 kHz RBW)

Pulse digitization uncertainty

(pulse response mode, PRF > 720/sweep time)

Log

Linear

RBW ≤ 1 MHz

< 1.25 dB pk-pk

< 4% of ref level

RBW = 2 MHz

< 3 dB pk-pk

< 12% of ref level

Standard Deviation (RBW < 1 MHz)

< 0.2 dB (nominal)

Time-gated spectrum analysis

Edge mode

Level mode

Range

3 µs to 65.535 ms

≤ 0.5 µs

Resolution

1 µs

Accuracy

±1 µs

(From GATE TRIGGER INPUT to positive edge of GATE OUTPUT)

Gate length

Range

1 µs to 65.535 ms

Resolution

1 µs

Accuracy

±1 µs

(From positive edge to negative edge of GATE OUTPUT)

7

1. Operation below 9 kHz requires Option 856xEC-006

2. Absolute flatness values referenced to 300 MHz CAL OUT

3. Typical values at 25 °C

4. Frequency reference accuracy = aging x time since last adjustment + initial achievable accuracy + temperature stability

5. Up to 1 µs jitter due to 1 µs resolution of gate delay clock