ADCLK950

Rev. 0 | Page 12 of 12

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

OUTLINE DIMENSIONS

1

40

10

11

29

28

20

19

3.05

2.90 SQ

2.75

TOP VIEW

6.00

BSC SQ

5.75

BSC SQ

COPLANARITY

0.08

4.50

REF

0.50

0.40

0.30

0.50

BSC

PIN 1

INDICATOR

0.60 MAX

0.60 MAX

0.25 MIN

EXPOSED

PAD

BOTTOM VIEW

PIN 1

INDICATOR

0.30

0.23

0.18

0.20 REF

12° MAX

0.80 MAX

0.65 TYP

1.00

0.85

0.80

0.05 MAX

0.02 NOM

SEATING

PLANE

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

Figure 24. 40-Lead Lead Frame Chip Scale Package [LF

CSP_VQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-40-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

ADCLK950BCPZ1

−40°C to +85°C

40-Lead LFCSP_VQ

CP-40-8

ADCLK950BCPZ-REEL71

−40°C to +85°C

40-Lead LFCSP_VQ

CP-40-8

ADCLK950/PCBZ1

Evaluation Board

©2009 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D08279-0-7/09(0)