ADIS16240

Rev. 0 | Page 4 of

16

TIMING SPECIFICATIONS

Table 2.

Parameter

Description

Min1

Typ

Max1

Unit

Serial clock rate2

0.01

2.5

MHz

Chip select period2

60

μs

Chip select to clock edge

120

ns

Data output valid after SCLK edge

30

ns

Data input setup time before SCLK rising edge

20

ns

Data input hold time after SCLK rising edge

20

ns

Data output fall time

10

25

ns

Data output rise time

10

25

ns

CS high after SCLK edge

430

ns

Timing Diagrams

CS

SCLK

Figure 2. SPI Chip Select Timing

CS

SCLK

DOUT

DIN

1

2

3

4

5

6

15

16

W/R

A5

A6

A4

A3

A2

D2

MSB

DB14

D1

LSB

DB13

DB12

DB10

DB11

DB2

LSB

DB1

Figure 3. SPI Timing (Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)