ADIS16265SLASHPCBZ datasheet(4/19 Pages) AD

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ADIS16260/ADIS16265

Preliminary Technical Data

Rev. PrB | Page 4 of 19

Parameter

Conditions

Min

Typ

Max

Unit

DAC OUTPUT

5 kΩ/100 pF to GND

Resolution

Bits

Relative Accuracy

For Code 101 to Code 4095

LSB

Differential Nonlinearity

LSB

Offset Error

±5

Gain Error

±0.5

Output Range

0 to 2.5

Output Impedance

Output Settling Time

μs

LOGIC INPUTS

Internal 3.3 V Interface

Input High Voltage, VINH

2.0

Input Low Voltage, VINL

0.8

For CS signal when used to wake up from sleep mode

0.55

Logic 1 Input Current, IINH

VIH = 3.3 V

±0.2

±10

μA

Logic 0 Input Current, IINL

VIL = 0 V

All except RST

−40

−60

μA

RST3

−1

Input Capacitance, CIN

DIGITAL OUTPUTS

Internal 3.3 V Interface

Output High Voltage, VOH

ISOURCE = 1.6 mA

2.4

Output Low Voltage, VOL

ISINK = 1.6 mA

0.4

SLEEP TIMER

Timeout Period4

0.5

128

sec

START-UP TIME

Initial

160

Sleep Mode Recovery

2.5

FLASH MEMORY

Endurance5

10,000

Cycles

Data Retention6

TJ = 55°C

Years

CONVERSION RATE

Minimum Conversion Time

0.488

Maximum Conversion Time

7.75

sec

Maximum Throughput Rate

2048

SPS

Minimum Throughput Rate

0.129

SPS

POWER SUPPLY

Operating Voltage Range, VCC

4.75

5.0

5.25

Power Supply Current

Normal mode at 25°C

TBD

Fast mode at 25°C

TBD

Sleep mode at 25°C

TBD

μA

1 ADIS16265 characterization data represents ±4σ to fall within the ±1% limit.

2 The sensor is capable of ±600°/sec, but the specifications herein are for ±320°/sec only.

3 The RST pin has an internal pull-up.

4 Guaranteed by design.

5 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.

6 Retention lifetime equivalent at junction temperature (TJ) 55°C, as per JEDEC Standard 22 Method A117. Retention lifetime decreases with junction temperature.

ADIS16265/PCBZ 数据表(PDF) 4 Page - Analog Devices

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