ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635

Rev. A | Page 13 of 16

ADP1043A

3.3V

VDD

PGND

PGND

FLAGIN

VDD

OTW

OTW

ADP3623/ADP3624/ADP3625/

ADP3633/ADP3634/ADP3635

ADP3623/ADP3624/ADP3625/

ADP3633/ADP3634/ADP3635

Figure 23. OTW

The

Signaling Scheme Example

OTW

The overtemperature shutdown turns off the device to protect it

in the event that the die temperature exceeds the absolute maxi-

mum limit in

open-drain configuration allows connection of

multiple devices to the same warning bus in a wire-OR’ed

configuration, as shown in Figure 23.

Table 2.

SUPPLY CAPACITOR SELECTION

local bypass capacitor is recommended to reduce the noise and

to supply some of the peak currents that are drawn.

An improper decoupling can dramatically increase the rise

times, cause excessive resonance on the OUTA and OUTB pins,

and, in some extreme cases, even damage the device, due to

inductive overvoltage on the VDD or OUTA/OUTB pins.

The minimum capacitance required is determined by the size

of the gate capacitances being driven, but as a general rule, a

4.7 µF, low ESR capacitor should be used. Multilayer ceramic

chip (MLCC) capacitors provide the best combination of low

ESR and small size. Use a smaller ceramic capacitor (100 nF)

with a better high frequency characteristic in parallel to the

main capacitor to further reduce noise.

Keep the ceramic capacitor as close as possible to the ADP362x/

ADP363x device, and minimize the length of the traces going

from the capacitor to the power pins of the device.

PCB LAYOUT CONSIDERATIONS

Use the following general guidelines when designing printed

circuit boards (PCBs):

•

Trace out the high current paths and use short, wide

(>40 mil) traces to make these connections.

•

Minimize trace inductance between the OUTA and OUTB

outputs and MOSFET gates.

•

Connect the PGND pin of the ADP362x/ADP363x device

as closely as possible to the source of the MOSFETs.

•

VDD and PGND pins.

•

Use vias to other layers, when possible, to maximize

thermal conduction away from the IC.

Figure 24 shows an example of the typical layout based on the

preceding guidelines.

Figure 24. External Component Placement Example

Note that the exposed pad of the package is not directly

connected to any pin of the package, but it is electrically and

thermally connected to the die substrate, which is the ground of

the device.

PARALLEL OPERATION

The two driver channels present in the ADP3623/ADP3633 or

ADP3624/ADP3634 devices can be combined to operate in

parallel to increase drive capability and minimize power

dissipation in the driver.

The connection scheme for the ADP3624/ADP3634 devices is

shown in Figure 25. In this configuration, INA and INB are

connected together, and OUTA and OUTB are connected

together.

Particular attention must be paid to the layout in this case to

optimize load sharing between the two drivers.

INA

VDD

PGND

ADP3624/ADP3634

OUTA

OUTB

INB

SD

OTW

1

3

8

7

6

5

A

B

2

4

Figure 25. Parallel Operation