SMB113A/B/SMB117/A

Preliminary Information

Summit Microelectronics, Inc

2111 2.4 6/24/2008

13

Note 5: Guaranteed by Design.

Figure 4 – I

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

100kHz

Symbol

Description

Conditions

Min

Typ

Max

Units

SCL clock frequency

0

100

kHz

Clock low period

4.7

µs

Clock high period

4.0

µs

Bus free time

Before new transmission –

Note 5

4.7

µs

Start condition setup time

4.7

µs

Start condition hold time

4.0

µs

Stop condition setup time

4.7

µs

Clock edge to data valid

SCL low to valid SDA (cycle

n)

0.2

3.5

µs

Data output hold time

SCL low (cycle n+1) to SDA

change

0.2

µs

SCL and SDA rise time

Note 5

1000

ns

SCL and SDA fall time

Note 5

300

ns

Data in setup time

250

ns

Data in hold time

0

ns

TI

Noise filter SCL and SDA

Noise suppression

136

ns

Write cycle time config

Configuration registers

10

ms

Write cycle time EE

Memory array

5

ms

t

R

t

F

t

HIGH

t

LOW

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

t

BUF

t

DH

t

AA

SCL

SDA

(IN)

SDA

(OUT)

t

WR (For Write Operation Only)

TIMING DIAGRAMS