STM32F102X4 datasheet(13/69 Pages) STMICROELECTRONICS

13 / 69 page

STM32F102x4, STM32F102x6

Description

Doc ID 15057 Rev 3

13/69

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

Embedded SRAM

4 or 6 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait

states.

Nested vectored interrupt controller (NVIC)

The STM32F102xx low-density USB access line embeds a nested vectored interrupt

controller able to handle up to 36 maskable interrupt channels (not including the 16 interrupt

lines of Cortex™-M3) and 16 priority levels.

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Closely coupled NVIC gives low latency interrupt processing

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Interrupt entry vector table address passed directly to the core

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Closely coupled NVIC core interface

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Allows early processing of interrupts

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Processing of late arriving higher priority interrupts

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Support for tail-chaining

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Processor state automatically saved

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Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detectors lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect external line with pulse

width lower than the Internal APB2 clock period. Up to 51 GPIOs are connected to the 16

external interrupt lines.

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example on

failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the configuration of the AHB frequency, the High Speed APB

(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and

the APB domains is 48 MHz. See Figure 2 for details on the clock tree.

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