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STM32F102C4 数据表(PDF) 43 Page - STMicroelectronics

部件名 STM32F102C4
功能描述  Low-density USB access line, ARM-based 32-bit MCU with 16/32 KB Flash, USB FS interface, 5 timers, ADC & 5 communication interfaces
PDF  69 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F102C4 数据表(HTML) 43 Page - STMicroelectronics

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STM32F102x4, STM32F102x6
Electrical characteristics
Doc ID 15057 Rev 3
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low-speed internal (LSI) RC oscillator
Wakeup time from low-power mode
The wakeup times given in Table 25 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
Stop or Standby mode: the clock source is the RC oscillator
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 8.
5.3.8
PLL characteristics
The parameters given in Table 26 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 8.
Table 24.
LSI oscillator characteristics (1)
1.
VDD = 3 V, TA = 40 to 85 °C unless otherwise specified.
Symbol
Parameter
Min(2)
2.
Based on characterization, not tested in production.
Typ
Max
Unit
fLSI
Frequency
30
40
60
kHz
tsu(LSI)
(3)
3.
Guaranteed by design, not tested in production.
LSI oscillator startup time
85
µs
IDD(LSI)
(3)
LSI oscillator power consumption
0.65
1.2
µA
Table 25.
Low-power mode wakeup timings
Symbol
Parameter
Typ
Unit
tWUSLEEP
(1)
1.
The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.
Wakeup from Sleep mode
1.8
µs
tWUSTOP
(1)
Wakeup from Stop mode (regulator in run mode)
3.6
µs
Wakeup from Stop mode (regulator in low-power
mode)
5.4
tWUSTDBY
(1)
Wakeup from Standby mode
50
µs
Table 26.
PLL characteristics
Symbol
Parameter
Value
Unit
Min(1)
Typ
Max(1)
fPLL_IN
PLL input clock(2)
18.0
25
MHz
PLL input clock duty cycle
40
60
%
fPLL_OUT
PLL multiplier output clock
16
48
MHz



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