STC3100

I2C interface

15/21

Values held in consecutive registers (such as the charge value in the REG_CHARGE_LOW

and REG_CHARGE_HIGH registers) must be read with a single I2C access to ensure data

integrity. It is possible to read multiple values in one I2C access, all values will be consistent.

The charge data is coded in 2’s complement format, and the LSB value is 6.70 uV.h.

The battery current is coded in 2’s complement format, and the LSB value is 11.77 uV. In

13-bit resolution mode, the 0 bit is always set to zero. In 12-bit resolution, bits 0 and 1 are

always set to zero.

The battery voltage is coded in binary format, and the LSB value is 2.44 mV.

The temperature value is coded in 2’s complement format, and the LSB value is 0.125° C.

The temperature of 0° C corresponds to code 0.

Table 10.

REG_MODE - address 0

Name

Pos.

Type

Def.

Description

SEL_EXT_CLK

0

R/W

0

32,768 Hz clock source:

0: auto-detect, 1: external clock

GG_RES

[2,1]

R/W

00

Gas gauge ADC resolution:

00:14 bits, 01:13 bits, 10:12 bits

GG_CAL

3

R/W

0

0: no effect

1: used to calibrate the AD converters

GG_RUN

4

R/W

0

0: standby mode. Accumulator and counter

registers are frozen, gas gauge and battery

monitor functions are in standby.

1: operating mode.

[7..5]

Unused

Table 11.

REG_CTRL - address 1

Name

Pos.

Type

Def.

Description

IO0DATA

0

RX

Port IO0 data status:

0 = IO0 input is low, 1 = IO0 input is high

W1

Port IO0 data output drive:

0 = IO0 output is driven low,1 = IO0 output is open

GG_RST

1

W

0

0: no effect

1: resets the charge accumulator and conversion

counter. GG_RST is a self-clearing bit.

GG_EOC

2

R

1

Set at the end of a battery current conversion

cycle. Clears upon reading.

VTM_EOC

3

R

1

Set at the end of a battery voltage or temperature

conversion cycle. Clears upon reading.

PORDET

4

R1

Power on reset (POR) detection bit:

0 = no POR event occurred,

1 = POR event occurred

W0

Soft reset:

0 = release the soft-reset and clear the POR

detection bit, 1 = assert the soft-reset and set the

POR detection bit.

[7..5]

Unused