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STM8L151C4U6 数据表(PDF) 85 Page - STMicroelectronics |
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STM8L151C4U6 数据表(HTML) 85 Page - STMicroelectronics |
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85 / 101 page  STM8L151xx, STM8L152xx Electrical parameters Doc ID 15962 Rev 2 85/101 INL Integral non linearity(7) RL ≥5kΩ, CL≤ 50 pF DACOUT buffer ON ± 2 TBD 12-bit LSB CL≤ 50 pF DACOUT buffer OFF TBD TBD Offset Offset error(8) RL ≥5kΩ, CL≤ 50 pF DACOUT buffer ON ± 20 TBD mV CL≤ 50 pF DACOUT buffer OFF TBD TBD Gain error Gain error RL ≥5kΩ, CL≤ 50 pF DACOUT buffer ON 0.5 TBD % CL≤ 50 pF DACOUT buffer OFF TBD TBD TUE Total unadjusted error RL ≥5kΩ, CL≤ 50 pF DACOUT buffer ON TBD TBD 12-bit LSB CL≤ 50 pF DACOUT buffer OFF TBD TBD tsettling Settling time (full scale: for a 12- bit input code transition between the lowest and the highest input codes when DAC_OUT reaches the final value ±1LSB RL ≥5kΩ, CL≤ 50 pF 7TBD µs Update rate Max frequency for a correct DAC_OUT (@95%) change when small variation of the input code (from code i to i+1LSB). RL ≥ 5kΩ, CL ≤50 pF 1 Msps tWAKEUP Wakeup time from OFF state. Input code between lowest and highest possible codes. RL ≥5kΩ, CL≤50 pF 9TBD µs PSRR+ Power supply rejection ratio (to VDDA) (static DC measurement ) RL≥ 5kΩ, CL≤50 pF -60 -35 dB 1. For 48-pin package only. 2. Data guaranteed by design, not tested in production. 3. Resistive load between DACOUT and GNDA. 4. Capacitive load at DACOUT pin. 5. It gives the output excursion of the DAC. 6. Difference between two consecutive codes - 1 LSB. 7. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023. 8. Difference between measured value and ideal value=VREF/2. Table 44. DAC characteristics, output on PF0(1) (continued) Symbol Parameter Conditions Min (2) Typ Max(1) Unit |
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