MCP3204 datasheet(21/40 Pages) MICROCHIP

21 / 40 page

DS21298E-page 21

MCP3204/3208

6.0

APPLICATIONS INFORMATION

6.1

Using the MCP3204/3208 with

Microcontroller (MCU) SPI Ports

With most microcontroller SPI ports, it is required to

send groups of eight bits. It is also required that the

microcontroller SPI port be configured to clock out data

on the falling edge of clock and latch data in on the

rising edge. Because communication with the

MCP3204/3208 devices may not need multiples of

eight clocks, it will be necessary to provide more clocks

than are required. This is usually done by sending

‘leading zeros’ before the start bit. As an example,

Figure 6-1 and Figure 6-2 illustrate how the MCP3204/

3208 can be interfaced to a MCU with a hardware SPI

port. Figure 6-1 depicts the operation shown in SPI

Mode 0,0, which requires that the SCLK from the MCU

idles in the ‘low’ state, while Figure 6-2 shows the

similar case of SPI Mode 1,1, where the clock idles in

the ‘high’ state.

As is shown in Figure 6-1, the first byte transmitted to

the A/D converter contains five leading zeros before

the start bit. Arranging the leading zeros this way

allows the output 12 bits to fall in positions easily

manipulated by the MCU. The MSB is clocked out of

the A/D converter on the falling edge of clock number

12. Once the second eight clocks have been sent to the

device, the MCU’s receive buffer will contain three

unknown bits (the output is at high impedance for the

first two clocks), the null bit and the highest order four

bits of the conversion. Once the third byte has been

sent to the device, the receive register will contain the

lowest order eight bits of the conversion results.

Employing this method ensures simpler manipulation

of the converted data.

Figure 6-2 shows the same thing in SPI Mode 1,1,

which requires that the clock idles in the high state. As

with mode 0,0, the A/D converter outputs data on the

falling edge of the clock and the MCU latches data from

the A/D converter in on the rising edge of the clock.

FIGURE 6-1:

SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).

678

10 11 12 13 14 15 16

SCLK

DIN

X = “Don’t Care” Bits

17 18 19 20 21 22 23 24

DOUT

NULL

BIT B11 B10 B9 B8

B6 B5 B4 B3 B2 B1 B0

HI-Z

MCU latches data from A/D

Data is clocked out of A/D

converter on falling edges

converter on rising edges of SCLK

Don’t Care

SGL/

DIFF

Start

B4 B3

B11 B10 B9

????

???

SGL/

DIFF

Start

Bit

(Null)

MCU Transmitted Data

(Aligned with falling

edge of clock)

MCU Received Data

(Aligned with rising

edge of clock)

Data stored into MCU receive

8 bits

Data stored into MCU receive

second 8 bits

Data stored into MCU receive

8 bits

Don’t Care

B7 B6 B5 B4 B3 B2 B1 B0

B11 B10 B9 B8

????

???

SGL/

DIFF

(Null)

MCP3204 数据表(PDF) 21 Page - Microchip Technology

MCP3204 数据表(HTML) 21 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

数据表下载

链接网址

MCP3204 数据表(PDF) 21 Page - Microchip Technology

MCP3204 数据表(HTML) 21 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

数据表 下载

链接网址

数据表下载