TC14433-ESLASHOG datasheet(8/24 Pages) MICROCHIP

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TC14433/A

DS21394D-page 8

4.0

DETAILED DESCRIPTION

The TC14433 CMOS IC becomes a modified dual-

slope A/D with a minimum of external components.

This IC has the customary CMOS digital logic circuitry,

as well as CMOS analog circuitry. It provides the user

with digital functions such as (counters, latches,

multiplexers),

and

analog

functions

such

(operational amplifiers and comparators) on a single

chip. Refer to the Functional Block diagram, Figure 4-3.

Features of the TC14433/A include auto-zero, high

input impedances and auto-polarity. Low power

consumption and a wide range of power supply

voltages are also advantages of this CMOS device.

The system’s auto-zero function compensates for the

offset voltage of the internal amplifiers and compara-

tors. In this “ratiometric system,” the output reading is

the ratio of the unknown voltage to the reference

voltage, where a ratio of 1 is equal to the maximum

count of 1999. It takes approximately 16,000 clock

periods to complete one conversion cycle. Each

conversion cycle may be divided into 6 segments.

Figure 4-1 shows the conversion cycle in 6 segments

for both positive and negative inputs.

FIGURE 4-1:

Integrator Waveforms at

Pin 6.

Segment 1 – The offset capacitor (CO), which compen-

sates for the input offset voltages of the buffer and

integrator amplifiers, is charged during this period.

However, the integrator capacitor is shorted. This

segment requires 4000 clock periods.

Segment 2 – During this segment, the integrator output

decreases to the comparator threshold voltage. At this

time, a number of counts equivalent to the input offset

voltage of the comparator is stored in the offset latches

for later use in the auto-zero process. The time for this

segment is variable and less than 800 clock periods.

Segment 3 – This segment of the conversion cycle is

the same as Segment 1.

Segment 4 – Segment 4 is an up going ramp cycle with

the unknown input voltage (VX as the input to the

integrator.

Figure 4-2

shows

the

equivalent

configuration of the analog section of the TC14433.

The actual configuration of the analog section is

dependent upon the polarity of the input voltage during

the previous conversion cycle.

FIGURE 4-2:

Equivalent Circuit Diagrams

of the Analog Section During Segment 4 of the

Timing Cycle

Segment 5 – This segment is a down-going ramp

period with the reference voltage as the input to the

integrator. Segment 5 of the conversion cycle has a

time equal to the number of counts stored in the offset

storage latches during Segment 2. As a result, the

system zeros automatically.

Segment 6 – This is an extension of Segment 5. The

time period for this portion is 4000 clock periods. The

results of the A/D conversion cycle are determined in

this portion of the conversion cycle.

Start

Typical

Positive

Input Voltage

Typical

Negative

Input Voltage

Time

Segment

Number

End

Comparator

Buffer

Integrator

–

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