MCP6L71RT-ESLASHMS datasheet(13/32 Pages) MICROCHIP

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DS22145A-page 13

MCP6L71/1R/2/4

4.0

APPLICATION INFORMATION

The

MCP6L71/1R/2/4

family

amps

manufactured using Microchip’s state of the art CMOS

process, specifically designed for low cost, low power

and general purpose applications. The low supply

voltage, low quiescent current and wide bandwidth

make the MCP6L71/1R/2/4 ideal for battery powered

applications.

4.1

Rail-to-Rail Inputs

4.1.1

PHASE REVERSAL

The MCP6L71/1R/2/4 op amps are designed to pre-

vent phase inversion when the input pins exceed the

supply voltages. Figure 2-10 shows an input voltage

exceeding both supplies without any phase reversal.

4.1.2

INPUT VOLTAGE AND CURRENT

LIMITS

In order to prevent damage and/or improper operation

of these amplifiers, the circuit they are in must limit the

currents (and voltages) at the input pins (see

Section 1.1

“Absolute

Maximum

Ratings

†”).

Figure 4-1 shows the recommended approach to pro-

tecting these inputs. The internal ESD diodes prevent

the input pins (VIN+ and VIN–) from going too far below

ground, and the resistors R1 and R2 limit the possible

current drawn out of the input pins. Diodes D1 and D2

prevent the input pins (VIN+ and VIN–) from going too

far above VDD, and dump any currents onto VDD.

FIGURE 4-1:

Protecting the Analog

Inputs.

A significant amount of current can flow out of the

inputs (through the ESD diodes) when the common

mode voltage (VCM) is below ground (VSS); see

Figure 2-7. Applications that are high impedance may

need to limit the usable voltage range.

4.1.3

NORMAL OPERATIONS

The input stage of the MCP6L71/1R/2/4 op amps uses

two differential CMOS input stages in parallel. One

operates at low common mode input voltage (VCM),

while the other at high VCM. With this topology, and at

room temperature, the device operates with VCM up to

0.3V above VDD and 0.3V below VSS (typically at

+25°C).

The transition between the two input stage occurs

when VCM = VDD – 1.1V. For the best distortion and

gain linearity, with non-inverting gains, avoid this region

of operation.

4.2

Rail-to-Rail Output

The output voltage range of the MCP6L71/1R/2/4 op

amps is VDD – 20 mV (minimum) and VSS +20mV

(maximum) when RL =10kΩ is connected to VDD/2

and VDD = 5.0V. Refer to Figure 2-13 for more informa-

tion.

4.3

Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response.

When driving large capacitive loads with these op

amps (e.g., > 100 pF when G = +1), a small series

resistor at the output (RISO in Figure 4-2) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitive load.

FIGURE 4-2:

Output Resistor, RISO

Stabilizes Large Capacitive Loads.

Bench measurements are helpful in choosing RISO.

Adjust RISO so that a small signal step response (see

Figure 2-15) has reasonable overshoot (e.g., 4%).

MCP6L7X

VDD

R1 >

VSS – (minimum expected V1)

2mA

VOUT

R2 >

VSS – (minimum expected V2)

2mA

RISO

VOUT

MCP6L7X

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