MCP6569-ESLASHST datasheet(20/44 Pages) MICROCHIP

20 / 44 page

MCP6566/6R/6U/7/9

DS22143B-page 20

4.6

PCB Surface Leakage

In applications where low input bias current is critical,

PCB (Printed Circuit Board) surface leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 1012

Ω. A 5V difference would

cause 5 pA of current to flow. This is greater than the

MCP6566/6R/6U/7/9 family’s bias current at +25°C

(1 pA, typical).

The easiest way to reduce surface leakage is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

An example of this type of layout is shown in

Figure 4-9.

FIGURE 4-9:

Example Guard Ring Layout

for Inverting Circuit.

Inverting Configuration (Figures 4-6 and 4-9):

Connect the guard ring to the non-inverting

input pin (VIN+). This biases the guard ring

to the same reference voltage as the

comparator (e.g., VDD/2 or ground).

Connect the inverting pin (VIN–) to the input

pad without touching the guard ring.

Non-inverting Configuration (Figure 4-4):

Connect the non-inverting pin (VIN+) to the

input pad without touching the guard ring.

Connect the guard ring to the inverting input

pin (VIN–).

4.7

PCB Layout Technique

When designing the PCB layout it is critical to note that

analog and digital signal traces are adequately

separated to prevent signal coupling. If the comparator

output trace is at close proximity to the input traces

then large output voltage changes from, VSS to VDD or

visa versa, may couple to the inputs and cause the

device output to oscillate. To prevent such oscillation,

the output traces must be routed away from the input

pins. The SC70-5 and SOT-23-5 are relatively immune

because the output pin OUT (pin 1) is separated by the

power pin VDD/VSS (pin 2) from the input pin +IN (as

long as the analog and digital traces remain separated

through out the PCB). However, the pinouts for the dual

and quad packages (SOIC, MSOP, TSSOP) have OUT

and -IN pins (pin 1 and 2) close to each other. The

recommended layout for these packages is shown in

Figure 4-10.

FIGURE 4-10:

Recommended Layout.

4.8

Unused Comparators

An unused amplifier in a quad package (MCP6569)

should be configured as shown in Figure 4-11. This

circuit prevents the output from toggling and causing

crosstalk. It uses the minimum number of components

and draws minimal current (see Figure 2-15 and

Figure 2-15).

FIGURE 4-11:

Unused Comparators.

Guard Ring

IN-

IN+

-INA

+INA

-INB

+INB

OUTB

OUTA

VSS

VDD

–

¼ MCP6569

MCP6569-E/ST 数据表(PDF) 20 Page - Microchip Technology

MCP6569-E/ST 数据表(HTML) 20 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载