MCP4641-104ESLASHML datasheet(14/92 Pages) MICROCHIP

14 / 92 page

MCP454X/456X/464X/466X

DS22107A-page 14

FIGURE 1-2:

I2C Bus Data Timing.

100

101

103

106

107

109

110

102

SCL

SDA

Out

TABLE 1-2:

I2C BUS DATA REQUIREMENTS (SLAVE MODE)

I2C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature

–40

°C ≤ TA ≤ +125°C (Extended)

Operating Voltage VDD range is described in AC/DC characteristics

Param.

No.

Sym

Characteristic

Min

Max

Units

Conditions

100

THIGH

Clock high time

100 kHz mode

4000

—

1.8V-5.5V

400 kHz mode

600

—

2.7V-5.5V

1.7 MHz mode

120

4.5V-5.5V

3.4 MHz mode

—

4.5V-5.5V

101

TLOW

Clock low time

100 kHz mode

4700

—

1.8V-5.5V

400 kHz mode

1300

—

2.7V-5.5V

1.7 MHz mode

320

4.5V-5.5V

3.4 MHz mode

160

—

4.5V-5.5V

Note 1:

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the

requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not

stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,

it must output the next data bit to the SDA line

TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I

2C bus specification) before

the SCL line is released.

The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between VIH

and VIL of the falling edge of the SCL signal. This specification is not a part of the I

2C specification, but

must be tested in order to ensure that the output data will meet the setup and hold specifications for the

receiving device.

Use Cb in pF for the calculations.

Not Tested

A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do

not unintentionally create a Start or Stop condition.

Ensured by the TAA 3.4 MHz specification test.

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