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MFRC52201HN1/TRAYB 数据表(PDF) 2 Page - NXP Semiconductors |
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MFRC52201HN1/TRAYB 数据表(HTML) 2 Page - NXP Semiconductors |
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2 / 96 page ![]() MFRC522_33 © NXP B.V. 2009. All rights reserved. Product data sheet PUBLIC Rev. 3 — 26 October 2009 112133 2 of 96 NXP Semiconductors MFRC522 Contactless reader IC N SPI up to 10 Mbit/s N I2C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode N RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin voltage supply I FIFO buffer handles 64 byte send and receive I Flexible interrupt modes I Hard reset with low power function I Power-down by software mode I Programmable timer I Internal oscillator for connection to 27.12 MHz quartz crystal I 2.5 V to 3.3 V power supply I CRC coprocessor I Programmable I/O pins I Internal self-test 4. Quick reference data [1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance. [2] VDDA, VDDD and VDD(TVDD) must always be the same voltage. [3] VDD(PVDD) must always be the same or lower voltage than VDDD. [4] Ipd is the total current for all supplies. [5] IDD(PVDD) depends on the overall load at the digital pins. [6] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2. [7] During typical circuit operation, the overall current is below 100 mA. [8] Typical value using a complementary driver configuration and an antenna matched to 40 Ω between pins TX1 and TX2 at 13.56 MHz. Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDDA analog supply voltage VDD(PVDD) ≤ VDDA = VDDD = VDD(TVDD); VSSA =VSSD =VSS(PVSS) =VSS(TVSS) =0V [1][2] 2.5 3.3 3.6 V VDDD digital supply voltage 2.5 3.3 3.6 V VDD(TVDD) TVDD supply voltage 2.5 3.3 3.6 V VDD(PVDD) PVDD supply voltage [3] 1.6 1.8 3.6 V VDD(SVDD) SVDD supply voltage VSSA =VSSD =VSS(PVSS) =VSS(TVSS) = 0 V 1.6 - 3.6 V Ipd power-down current VDDA =VDDD = VDD(TVDD) =VDD(PVDD) =3V hard power-down; pin NRSTPD set LOW [4] --5 µA soft power-down; RF level detector on [4] --10 µA IDDD digital supply current pin DVDD; VDDD = 3 V - 6.5 9 mA IDDA analog supply current pin AVDD; VDDA = 3 V, CommandReg register’s RcvOff bit = 0 - 7 10 mA pin AVDD; receiver switched off; VDDA =3V, CommandReg register’s RcvOff bit = 1 -3 5 mA IDD(PVDD) PVDD supply current pin PVDD [5] - - 40 mA IDD(TVDD) TVDD supply current pin TVDD; continuous wave [6][7][8] - 60 100 mA Tamb ambient temperature HVQFN32 −25 - +85 °C |
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