MPC8533VTALFB datasheet(65/116 Pages) FREESCALE

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MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

16.2.3

Interfacing With Other Differential Signaling Levels

With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are HCSL

(high-speed current steering logic) compatible DC-coupled.

Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can be

used but may need to be AC-coupled due to the limited common mode input range allowed (100 to

400 mV) for DC-coupled connection.

LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock

driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to

AC-coupling.

NOTE

Figure 45 through Figure 48 are for conceptual reference only. Due to the

fact that clock driver chip's internal structure, output impedance and

termination requirements are different between various clock driver chip

manufacturers, it is very possible that the clock circuit reference designs

provided by clock driver chip vendor are different from what is shown

below. They might also vary from one vendor to the other. Therefore,

Freescale Semiconductor can neither provide the optimal clock driver

reference circuits, nor guarantee the correctness of the following clock

driver connection reference circuits. The system designer is recommended

to contact the selected clock driver chip vendor for the optimal reference

circuits with the MPC8533E SerDes reference clock receiver requirement

provided in this document.

Figure 45 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It

assumes that the DC levels of the clock driver chip is compatible with MPC8533E SerDes reference clock

input’s DC requirement.

Figure 45. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

n_REF_CLK

Clock Driver

100

Ω differential PWB trace

Clock driver vendor dependent

source termination resistor

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

HCSL CLK Driver Chip

Total 50

Ω. Assume clock driver’s

output impedance is about 16

Ω.

MPC8533EMP

CLK_Out

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