MPC8378CVRALFA datasheet(29/126 Pages) FREESCALE

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MPC8378E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

Figure 10 shows the SGMII receiver input compliance mask eye diagram.

Figure 10. SGMII Receiver Input Compliance Mask

8.3.2

AC Requirements for SGMII L1_SD_REF_CLK and L1_SD_REF_CLK

Table 29 lists the AC timing specifications. Note that L1_SD_REF_CLK and L1_SD_REF_CLK are not

intended to be used with, and should not be clocked by, a spread spectrum clock source.

Table 29. L1_SD_REF_CLK and L1_SD_REF_CLK AC Requirements

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

L1_SD_REF_CLK/_B reference clock cycle time

100 MHz

125 MHz

tCK_REF

—

—ns

L1_SD_REF_CLK/_B rise/fall time (80%-20%)

tCK_RISE/tCK_FALL

——

—

L1_SD_REF_CLK/_B duty cycle (@50% L1_

nVDD)tck_dty

45%

—

55%

—

L1_SD_REF_CLK/_B cycle to cycle clock jitter (period

jitter)

tCKCJ

—

100

—

L1_SD_REF_CLK/_B phase jitter peak-to-peak.

Deviation in edge location with respect to mean edge

location.

tCKPJ

–50

—

Note:

1 Both options provide serial interface bit rate of 1.25 Gbps. 8 ns only applies when 125 MHz SerDes1 clock frequency is

selected during POR.

Tolerance of ±100 ppm.

0.275

0.4

0.6

0.725

VRX_DIFFp-p-max/2

VRX_DIFFp-p-min/2

–VRX_DIFFp-p-min/2

–VRX_DIFFp-p-max/2

Time (UI)

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