PCIMX515CJM6C datasheet(21/184 Pages) FREESCALE

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Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

3.2.1

Power-Up Sequence

Figure 2 shows the power-up sequence.

Figure 2. Power-Up Sequence

NOTE

The POR_B input must be immediately asserted at power-up and remain

asserted until after the last power rail is at its working voltage.

3.2.2

Power-Down Sequence

The following power-down sequence is recommend for the i.MX51 processor:

•

To be provided.

3.3

I/O DC Parameters

This section includes the DC parameters of the following I/O types:

•

General Purpose I/O and High-Speed General Purpose I/O (GPIO/HSGPIO)

•

Double Data Rate 2 (DDR2)

•

Low Voltage I/O (LVIO)

•

Ultra High Voltage I/O (UHVIO)

•

High-Speed I2C and I2C

•

Enhanced Secure Digital Host Controller (eSDHC)

AHVDDRGB

NVCC_TV_BACK

TVDAC_DHVDD

VDD_DIG_PLL_A/B

VDD_ANA_PLL_A/B

NVCC_OSC

NVCC_USBPHY

VDDA33

NVCC_EMI_DRAM

NVCC_SRTC_POW

VDDA

NVCC_NANDF_x

NVCC_PER15

NVCC_PER17

NVCC_HS4_1

NVCC_HS4_2

NVCC_HS6

NVCC_HS10

NVCC_PERx2

NVCC_EMI

NVCC_IPU

NVCC_I2C

VDDGP4

VDD_FUSE1

VCC

1. VDD_FUSE should only be powered when writing.

2. NVCC_PERx refers to NVCC_PER 3, 5, 8, 9, 10, 11, 12, 13, 14.

3. No power-up sequence dependencies exist between the supplies shown in the block diagram shaded in gray.

4. There is no requirement for VDDGP to be preceded by any other power supply other than NVCC_SRTC_POW.

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