MPC8378CVRAGDA datasheet(77/126 Pages) FREESCALE

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MPC8378E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

SPI

Figure 51 provides the AC test load for the SPI.

Figure 51. SPI AC Test Load

Figure 52 through Figure 53 represent the AC timing from Table 65. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Figure 52 shows the SPI timing in slave mode (external clock).

Figure 52. SPI AC Timing in Slave Mode (External Clock) Diagram

SPI inputs—Slave mode (external clock) input hold time

tNEIXKH

2—

Note:

1 The symbols used for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the internal

timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).

2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings

are measured at the pin. The maximum SPICLK input frequency is 66.666 MHz.

Table 65. SPI AC Timing Specifications (continued)

Parameter

Symbol1

Min

Max

Unit

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

SPICLK (input)

tNEIXKH

tNEIVKH

tNEKHOV

Input Signals:

SPIMOSI

(See Note)

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

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