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MPC8378CVRAGDA 数据表(PDF) 105 Page - Freescale Semiconductor, Inc |
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MPC8378CVRAGDA 数据表(HTML) 105 Page - Freescale Semiconductor, Inc |
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105 / 126 page ![]() MPC8378E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 105 Package and Pin Listings GVDD A2, D2, R2, U2, AC2, AF2, AJ2, F3, H3, L3, N3, Y3, AB3, B4, P4, AF4, AH4, C5, F5, K5, V5, AA5, AD5, N6, R6, AJ6, B7, E7, K7, AA7, AE7, AG7, AD8 Power for DDR SDRAM I/O Voltage (2.5 or 1.8 V) GVDD — OVDD AC10, D12, AF12, AJ12, K23, Y23, R24, AD24, L25, W25, AB26, U27, M28, Y28, G10, A11, C11 PCI, USB, and other Standard (3.3 V) OVDD — No Connect NC F16, F17, AD16, AD17 — — 8 Pull Down Pull Down B16, AH18 — — 7 Note: 1 This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD. 2 This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OVDD. 3 This output is actively driven during reset rather than being released to high impedance during reset. 4 These JTAG pins have weak internal pull-up P-FETs that are always enabled. 5 This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI Specification recommendation and see AN3665, MPC837xE Design Checklist, for more details. 6 These are On Die Termination pins, used to control DDR2 memories internal termination resistance. 7 This pin must always be tied to GND using a 0 Ω resistor. 8 This pin must always be left not connected. 9 For DDR2 operation, it is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω resistor. 10 This pin must always be tied low. If it is left floating it may cause the device to malfunction. 11 See AN3665, “MPC837xE Design Checklist,” for proper DDR termination. 12 This pin must not be pulled down during PORESET. 13 Open or tie to GND. Table 67. TePBGA II Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply Notes |
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