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MPC8378CVRAFDA 数据表(PDF) 50 Page - Freescale Semiconductor, Inc |
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MPC8378CVRAFDA 数据表(HTML) 50 Page - Freescale Semiconductor, Inc |
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50 / 126 page ![]() MPC8378E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2 50 Freescale Semiconductor Enhanced Secure Digital Host Controller (eSDHC) Figure 30 provides the eSDHC clock input timing diagram. Figure 30. eSDHC Clock Input Timing Diagram Input hold times: SD_CMD, SD_DAT x, SD_CD to SD_CLK tSFSIXKH 0— ns 2 SD_CLK delay within device tINT_CLK_DLY 1.5 — ns 4 Output valid: SD_CLK to SD_CMD, SD_DAT x valid tSFSKHOV —4 ns 2 Output hold: SD_CLK to SD_CMD, SD_DAT x valid tSFSKHOX 0— — — SD card input setup tISU 5— ns 3 SD card input hold tIH 5— ns 3 SD card output valid tODLY —14 ns 3 SD card output hold tOH 0— ns 3 Notes: 1 The symbols used for timing specifications herein follow the pattern of t (first three letters of functional block)(signal)(state) (reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going to high (H). Also tSFSKHOV symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with respect to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2 Measured at capacitive load of 40 pF. 3 For reference only, according to the SD card specifications. 4 Average, for reference only. Table 46. eSDHC AC Timing Specifications for Full-Speed Mode (continued) At recommended operating conditions OVDD = 3.3 V ± 165 mV. Parameter Symbol 1 Min Max Unit Notes eSDHC tSFSCKR External Clock VM VM VM tSFSCK tSFSCKF VM = Midpoint Voltage (OVDD/2) operational mode tSFSCKL tSFSCKH |
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