MPC8533VTAAJB datasheet(36/116 Pages) FREESCALE

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MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC), MII Management

Figure 19 shows the RMII transmit AC timing diagram.

Figure 19. RMII Transmit AC Timing Diagram

8.5.5.2

RMII Receive AC Timing Specifications

Table 34 shows the RMII receive AC timing specifications.

REF_CLK to RMII data TXD[1:0], TX_EN delay

tRMTDX

1.0

—

10.0

—

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit

timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,

the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.

For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

Table 34. RMII Receive AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5%.or 2.5 V ± 5%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Notes

REF_CLK clock period

tRMR

15.0

20.0

25.0

—

REF_CLK duty cycle

tRMRH

—

REF_CLK peak-to-peak jitter

tRMRJ

——

250

—

Rise time REF_CLK (20%–80%)

tRMRR

1.0

—

2.0

—

Fall time REF_CLK (80%–20%)

tRMRF

1.0

—

2.0

—

RXD[1:0], CRS_DV, RX_ER setup time to

REF_CLK rising edge

tRMRDV

4.0

—

Table 33. RMII Transmit AC Timing Specifications (continued)

At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Notes

REF_CLK

TXD[1:0]

tRMTDX

tRMT

tRMTH

tRMTR

tRMTF

TX_EN

TX_ER

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