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33784 数据表(PDF) 8 Page - Freescale Semiconductor, Inc

部件名 33784
功能描述  DSI 2.02 Sensor Interface
PDF  30 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

33784 数据表(HTML) 8 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
8
Freescale Semiconductor
33784
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions -0.3V
≤ VBUSIN or VBUSOUT ≤ 30V, 6.0V ≤ VH_CAP ≤ 30V, -40°C ≤ TA ≤ 125°C,
AGND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Internal Oscillator Frequency
fOSC
9.0
10.0
11.0
MHz
Internal Oscillator Duty Cycle
DCOSC
45
50
55
%
Initialization to Bus Switches Close
tBS
–
–
50
μs
Communication Data Rate
DRATE
100
–
200
kbps
Loss of Signal Reset Time(9)
Maximum Time for BUSIN to Be Below Frame Threshold
tTO
2.0
–
4.0
ms
ADC Code Conversion Time(10)
tADC
–
–
20
μs
BUSIN Response Current Slew Rate
1.0mA to 9.0mA Transition Rise
9.0mA to 1.0mA Transition Fall
tITR_R
tITR_F
–
–
–
–
8.0
8.0
mA/
μs
BUSIN Timing to Response Current
BUSIN Negative Voltage Transition = 3.0V to IRSP = 7.0mA Rise
TA = -40°C
TA = +25°C
TA =+125°C
BUSIN Negative Voltage Transition = 3.0V to IRSP = 5.0mA Fall
tRSP_R
tRSP_F
–
–
–
–
–
–
–
–
2.5
2.5
3.0
2.5
μs
Bus Signal Duty Cycle(9)
Logic [0] (~ 1/3 + 20%)
Logic [1] (~ 2/3 + 20%)
DCL
DCH
25
54
33
67
40
80
%
I/O Transition Time (CLoad = 50pF)(9)
tTRIO
–
–
100
ns
I/O Delay from Input State Change to Status Register Valid(9)
tINDLYIO
–
–
300
ns
I/O Delay from DBUS Command to I/O Output State Change
tOUTDLYIO
–
11.5
15
μs
Delay from I/O1 Rising Edge to ADC Value = 3F8(9)
tADCDIS
–
–
300
ns
HCAP tPOR Mask
ON (rising edge)
OFF (falling edge)
tPORMASKHCAP
(ON)
tPORMASKHCAP
(OFF)
2.0
1.0
5.0
3.5
9.0
8.0
μs
REGOUT tPOR Mask
ON (rising edge)
OFF (falling edge)
tPORMASKREG
OUT(ON)
tPORMASKREG
OUT(OFF)
2.0
1.0
5.0
3.5
9.0
8.0
μs
Notes
9.
Assured by design.
10.
Assured by design. Conversion is started and completed during idle time.



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