AD6657BBCZ datasheet(19/32 Pages) AD

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AD6657

Rev. 0 | Page 19 of 32

If a low jitter clock source is not available, another option is to

ac-couple a differential PECL signal to the sample clock input

pins, as shown in Figure 39. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent

jitter performance.

100Ω

0.1µF

240Ω

PECL DRIVER

50kΩ

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

AD951x

ADC

Figure 39. Differential PECL Sample Clock (Up to 625 MHz)

A third option is to ac-couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 40. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock

drivers offer excellent jitter performance.

100Ω

0.1µF

50kΩ

CLK–

CLK+

ADC

CLOCK

INPUT

CLOCK

INPUT

AD951x

LVDS DRIVER

Figure 40. Differential LVDS Sample Clock (Up to 625 MHz)

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended CMOS signal. In such applica-

tions, the CLK+ pin should be driven directly from a CMOS

gate, and the CLK− pin should be bypassed to ground with a

0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 41).

OPTIONAL

100Ω

0.1µF

39kΩ

50Ω1

150Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

VCC

1kΩ

CLOCK

INPUT

AD951x

CMOS DRIVER

Figure 41. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

CLK+ can be driven directly from a CMOS gate. Although

the CLK+ input circuit supply is AVDD (1.8 V), this input is

designed to withstand input voltages of up to 3.6 V, making the

selection of the drive logic voltage very flexible (see Figure 42).

150Ω RESISTOR IS OPTIONAL.

OPTIONAL

100Ω

0.1µF

VCC

50Ω1

CLK–

CLK+

ADC

1kΩ

CLOCK

INPUT

AD951x

CMOS DRIVER

Figure 42. Single-Ended 3.3 V CMOS Input Clock (Up to 200 MHz)

Input Clock Divider

The AD6657 contains an input clock divider with the ability to

divide the input clock by integer values from 1 to 8.

The AD6657 clock divider can be synchronized using the

external SYNC input. Bit 1 of Register 0x3A enables the clock

divider to be resynchronized on every SYNC signal. A valid

SYNC causes the clock divider to reset to its initial state. This

synchronization feature allows multiple parts to have their clock

dividers aligned to guarantee simultaneous input sampling.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate

a variety of internal timing signals and, as a result, may be

sensitive to clock duty cycle. Commonly, a ±5% tolerance is

required on the clock duty cycle to maintain dynamic

performance characteristics.

The AD6657 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock signal

with a nominal 50% duty cycle. This allows the user to provide a

wide range of clock input duty cycles without affecting the per-

formance of the AD6657. Noise and distortion performance are

nearly flat for a wide range of duty cycles with the DCS enabled.

Jitter in the rising edge of the input is still of paramount concern

and is not easily reduced by the internal stabilization circuit. The

duty cycle control loop does not function for clock rates less

than 40 MHz nominally. The loop has a time constant asso-

ciated with it that must be considered in applications in which

the clock rate can change dynamically. A wait time of 1.5 μs to

5 μs is required after a dynamic clock frequency increase or

decrease before the DCS loop is relocked to the input signal.

During the time period that the loop is not locked, the DCS

loop is bypassed, and internal device timing is dependent on the

duty cycle of the input clock signal.

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