AD8432

Rev. 0 | Page 18 of 28

THEORY OF OPERATION

LOW NOISE AMPLIFIER (LNA)

The AD8432 is a dual-channel, ultralow noise amplifier with

integrated pin-strappable, gain-setting resistors. The resistors

can be externally connected to achieve differential gains of

12.04 dB, 18.06 dB, 21.58 dB, and 24.08 dB (×4, ×8, ×12, and

×16). A simplified schematic of a LNA is shown in Figure 60.

The LNA is driven with a single-ended input and measured

differentially at the output. The inverting input INL must be

ac-coupled to ground through a capacitor for proper operation.

The LNA cannot be driven differentially due to the asymmetry

of the internal gain setting resistors. The gain from the inverting

input INL to the single-ended output (OPH or OPL) does not

match the gain from the noninverting input INH to the single-

ended output.

The AD8432 inputs have a dc bias voltage of 3.25 V, which is

generated internally. The inputs must be ac-coupled through a

series capacitor to maintain the dc bias level of the inputs. Likewise,

the AD8432 outputs have a dc bias voltage of 2.5V. An ac coupling

capacitor in series with each connection is recommended to

prevent improper loading of the outputs.

The AD8432 supports a differential output voltage of 4.8 V p-p

for the common-mode output voltage of 2.5 V. Therefore, for a

differential gain G = 12.04 dB, the maximum input voltage allowed

is 1.2 V p-p.

Clamping the inputs ensures quick recovery from large input

voltages. The input back-to-back diodes, which are integrated

inside the die (IND1 and IND2), should be used for the lowest gain

configuration (12.04 dB) to protect the input from overdriving.

They should be connected after the source resistance or before

the INH coupling capacitor.

The use of a fully differential topology and negative feedback

minimizes distortion. A differential signal enables smaller swings at

each output, which results in reduction of third-order distortion.

The AD8432 is a voltage feedback amplifier. Due to gain band-

width product (GBW), a decrease in bandwidth should be

expected as the gain increases. Table 5 displays the values of −3 dB

bandwidth for each gain with unterminated input impedance.

GAIN SETTING TECHNIQUE

Pin strapping is used to set the gain of the amplifier. Gain setting

resistors are integrated in the LNA and are accessible externally

through the GOH, GMH, GML, and GOL pins. By externally

shorting these pins, and thereby shorting or connecting the

internal resistors, the AD8432 can be configured for four different

gains. Table 5 shows which pins must be connected to achieve

the desired gain.

RG2

12

Ω

RG3

24

Ω

RG4

48

Ω

RG7

48

Ω

RG6

24

Ω

RG5

24

Ω

RG1

12

Ω

I

I

I

I

CINH

INH

OPH

VPS

OPL

INL

Q2

Q1

GMH

GOH

GML

GOL

CINL

GND

GND

GND

RSH

RS

CSH

VS

Figure 60. Simplified Schematic of LNA

Table 5. Gain Setting Using Pin-Strapping Technique and −3 dB Bandwidth for Each Gain Configuration

Differential

Gain (dB)

Single

Gain (dB)

−3 dB

BW (MHz)

RG1 (Ω)

RG2 (Ω)

RG3 (Ω)

RG4 (Ω)

RG5 (Ω)

RG6 (Ω)

RG7 (Ω)

12.04

6.02

200

12

12

Connect

GMH to GOH

Connect

GOH to OPH

24

Connect

GML to GOL

Connect

GOL to OPL

18.06

12.04

90

12

12

24

Connect

GOH to OPH

24

24

Connect

GOL to OPL

21.58

15.56

50

12

12

Connect

GMH to GOH

48

24

Connect

GML to GOL

48

24.08

18.06

32

12

12

24

48

24

24

48