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ADP3629ARMZ-R7 数据表(PDF) 13 Page - Analog Devices |
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ADP3629ARMZ-R7 数据表(HTML) 13 Page - Analog Devices |
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13 / 16 page ![]() ADP3629/ADP3630/ADP3631 Rev. 0 | Page 13 of 16 THERMAL CONSIDERATIONS When designing a power MOSFET gate drive, the maximum power dissipation in the driver must be considered to avoid exceeding the maximum junction temperature. Data on package thermal resistance is provided in Table 3 to help the designer in this task. Several equally important aspects must also be considered. • Gate charge of the power MOSFET being driven • Bias voltage value used to power the driver • Maximum switching frequency of operation • Value of external gate resistance • Maximum ambient (and PCB) temperature • Type of package All of these factors influence and limit the maximum allowable power dissipated in the driver. The gate of a power MOSFET has a nonlinear capacitance characteristic. For this reason, although the input capacitance is usually reported in the MOSFET data sheet as CISS, it is not useful to calculate power losses. The total gate charge necessary to turn on a power MOSFET device is usually reported on the device data sheet under QG. This parameter varies from a few nanocoulombs (nC) to several hundreds of nC and is specified at a specific VGS value (10 V or 4.5 V). The power necessary to charge and then discharge the gate of a power MOSFET can be calculated as follows: PGATE = VGS × QG × fSW where: VGS is the bias voltage powering the driver (VDD). QG is the total gate charge. fSW is the maximum switching frequency. The power dissipated for each gate (PGATE) must be multiplied by the number of drivers (in this case, 1 or 2) being used in each package; this PGATE value represents the total power dissipated in charging and discharging the gates of the power MOSFETs. Not all of this power is dissipated in the gate driver because part of it is actually dissipated in the external gate resistor, RG. The larger the external gate resistor, the smaller the amount of power that is dissipated in the gate driver. In modern switching power applications, the value of the gate resistor is kept at a minimum to increase switching speed and to minimize switching losses. In all practical applications where the external resistor is in the order of a few ohms, the contribution of the external resistor can be ignored, and the extra loss is assumed to be in the driver, providing a good guard band for the power loss calculations. In addition to the gate charge losses, there are also dc bias losses (PDC) due to the bias current of the driver. This current is present regardless of the switching frequency. PDC = VDD × IDD The total estimated loss is the sum of PDC and PGATE. PLOSS = PDC + (n × PGATE) where n is the number of gates driven. When the total power loss is calculated, the temperature increase can be calculated as follows: ΔTJ = PLOSS × θJA Design Example For example, consider driving two IRFS4310Z MOSFETs with a VDD of 12 V at a switching frequency of 100 kHz, using an ADP3630 in the MSOP package. The maximum PCB temperature considered for this design is 85°C. From the MOSFET data sheet, the total gate charge is QG = 120 nC. PGATE = 12 V × 120 nC × 100 kHz = 144 mW PDC = 12 V × 1.2 mA = 14.4 mW PLOSS = 14.4 mW + (2 × 144 mW) = 302.4 mW The MSOP thermal resistance is 162.2°C/W (see Table 3). ΔTJ = 302.4 mW × 162.2°C/W = 49.0°C TJ = TA + ΔTJ = 134.0°C ≤ TJ_MAX This estimated junction temperature does not factor in the power dissipated in the external gate resistor and, therefore, provides a certain guard band. If a lower junction temperature is required by the design, the SOIC_N package, which provides a thermal resistance of 110.6°C/W, can be used. Using the SOIC_N package, the maximum junction temperature is ΔTJ = 302.4 mW × 110.6°C/W = 33.4°C TJ = TA + ΔTJ = 118.4°C ≤ TJ_MAX Other options to reduce power dissipation in the driver include reducing the value of the VDD bias voltage, reducing the switching frequency, and choosing a power MOSFET with a smaller gate charge. |
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