ADP3629/ADP3630/ADP3631

Rev. 0 | Page 12 of 16

OVERTEMPERATURE PROTECTIONS

The ADP3629/ADP3630/ADP3631 provide two levels of over-

temperature protection:

•

Overtemperature warning (OTW)

•

Overtemperature shutdown

The overtemperature warning is an open-drain logic signal and

is active low. In normal operation, when no thermal warning is

present, the signal is high, whereas when the warning threshold

is crossed, the signal is pulled low.

ADP1043

3.3V

VDD

PGND

PGND

FLAGIN

VDD

OTW

OTW

ADP3629/ADP3630/ADP3631

ADP3629/ADP3630/ADP3631

Figure 23. OTW Signaling Scheme Example

The OTW open-drain configuration allows the connection

of multiple devices to the same warning bus in a wire-OR’ed

configuration, as shown in

.

Figure 23

The overtemperature shutdown turns off the device to protect it

in the event that the die temperature exceeds the absolute maxi-

mum limit of 150°C (see Table 2).

SUPPLY CAPACITOR SELECTION

A local bypass capacitor for the supply input (VDD) of the

ADP3629/ADP3630/ADP3631 is recommended to reduce the

noise and to supply some of the peak currents that are drawn.

An improper decoupling can dramatically increase the rise times,

cause excessive resonance on the OUTA and OUTB pins, and, in

some extreme cases, even damage the device due to inductive

overvoltage on the VDD or OUTA/OUTB pins.

The minimum capacitance required is determined by the size of

the gate capacitances being driven, but as a general rule, a 4.7 μF,

low ESR capacitor should be used. Multilayer ceramic chip

(MLCC) capacitors provide the best combination of low ESR

and small size. To further reduce noise, use a smaller ceramic

capacitor (100 nF) with a better high frequency characteristic

in parallel with the main capacitor.

Place the ceramic capacitor as close as possible to the ADP3629/

ADP3630/ADP3631 device and minimize the length of the

traces going from the capacitor to the power pins of the device.

PCB LAYOUT CONSIDERATIONS

Use the following general guidelines when designing printed

circuit boards (PCBs) for the ADP3629/ADP3630/ADP3631:

•

Trace out the high current paths and use short, wide

(>40 mil) traces to make these connections.

•

Minimize trace inductance between the OUTA and OUTB

outputs and the MOSFET gates.

•

Connect the PGND pin as close as possible to the source of

the MOSFETs.

•

Place the VDD bypass capacitor as close as possible to the

VDD and PGND pins.

•

When possible, use vias to other layers to maximize thermal

conduction away from the IC.

Figure 24 shows an example of the typical layout based on the

preceding guidelines.

Figure 24. External Component Placement Example

PARALLEL OPERATION

The two driver channels in the ADP3629 and ADP3630 devices

can be combined to operate in parallel to increase drive capability

and minimize power dissipation in the driver.

The connection scheme for the ADP3630 is shown in Figure 25.

In this configuration, INA and INB are connected together, and

OUTA and OUTB are connected together.

Particular attention must be paid to the layout in this case to

optimize load sharing between the two drivers.

INA

VDD

PGND

ADP3630

OUTA

OUTB

INB

SD

OTW

1

3

8

7

6

5

A

B

2

4

Figure 25. Parallel Operation