LTM8027

14

8027f

APPLICATIONS INFORMATION

a 15V minimum input voltage)

R

14.5V

1.4V

–1

⎛

⎝⎜

⎞

⎠⎟

= 464k

through a large value pull-up resistor. This pin contains

a low impedance clamp at 6V, so the RUN pin will sink

I

V

R

PU

Because this arrangement will clamp the RUN pin to 6V,

it will violate the 5V absolute maximum voltage rating of

the pin. This is permitted, however, as long as the absolute

maximum input current rating of 1mA is not exceeded.

Input RUN pin currents of <100μA are recommended: a

1M or greater pull-up resistor is typically used for this

configuration.

Soft-Start

1.231V

The amount of time in which the power supply must be

before the SS pin voltage enters its active region is ap-

proximated by the following formula:

50µA

Hot-Plugging Safely

The small size, robustness and low impedance of ceramic

capacitors make them an attractive option for the input

bypass capacitor of LTM8027. However, these capacitors

can cause problems if the LTM8027 is plugged into a live

supply (see Linear Technology Application Note 88 for

a complete discussion). The low loss ceramic capacitor

combined with stray inductance in series with the power

source forms an under damped tank circuit, and the volt-

nominal input voltage, possibly exceeding the LTM8027’s

rating and damaging the part. If the input supply is poorly

controlled or the user will be plugging the LTM8027 into an

energized supply, the input network should be designed to

prevent this overshoot by introducing a damping element

into the path of current flow. This is often done by adding

an inexpensive electrolytic bulk capacitor across the input

terminals of the LTM8027. The criteria for selecting this

capacitor is that the ESR is high enough to damp the ringing,

and the capacitance value is several times larger than the

LTM8027 ceramic input capacitor. The bulk capacitor does

not need to be located physically close to the LTM8027;

it should be located close to the application board’s input

connector, instead.

Synchronization

The oscillator can be synchronized to an external clock.

at least 10% below the desired synchronization frequency.

It is recommended that the SYNC pin be driven with a

square wave that has amplitude greater than 2.3V, pulse

width greater than 1μs and rise time less than 500ns. The

rising edge of the sync wave form triggers the discharge

of the internal oscillator capacitor.