5075 series

SEIKO NPC CORPORATION —3

PAD LAYOUT

(Unit:

µm)

PAD DIMENSIONS

PIN DESCRIPTION

BLOCK DIAGRAM

I

5075A

× (for Flip Chip Bonding)

I

5075B

× (for Wire Bonding)

Chip size: 0.84

× 0.69mm

Chip thickness: 130µm ± 15µm

PAD size: 90µm

× 90µm

Chip size: 0.84

× 0.69mm

Chip thickness: 130µm ± 15µm

PAD size: 90µm

× 90µm

Pad No.

Pad dimensions [µm]

Pad No.

Pin

I/O

Description

X

Y

5075A

× 5075B×

1

–189

–240

1

2

XT

I

Crystal connection pin (amplifier input)

2

189

–240

2

1

XTN

O

Crystal connection pin (amplifier output)

3

315

–21

3

6

VDD

–

(+) supply pin

4

315

225

4

5

Q

O

Clock output pin

5

–315

225

5

4

VSS

–

(

−) supply pin

6

–315

–21

6

3

VC

I

Oscillation frequency control voltage input pin (positive polarity)

(frequency increases with increasing voltage)

*1. N = 1, 2, 4, 8, 16

XT

XTN

VDD

Q

VC

VSS

X

Y

(420, 345)

(

−420, −345)

12

3

4

6

5

(0,0)

XTN

XT

VC

VSS

VDD

Q

X

Y

(420, 345)

(

−420, −345)

12

3

4

6

5

(0,0)

1

N

VSS

Oscillation

Detector

Q

Voltage

Regulator

XT

VDD

XTN

VC

Level Shifter

CMOS ouput

Buffer

*1