ICS9P936 datasheet(7/12 Pages) IDT

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IDTTM/ICSTM

Low Skew Dual Bank DDR I/II Fan-out Buffer

1084C 12/03/09

ICS9P936

Low Skew Dual Bank DDR I/II Fan-out Buffer

Timing Requirements VDDQ2.5/1.8 = 2.5V +/- 0.2V

TA = 0 - 70°C Supply Voltage AVDD2.5 = 2.5V+/-0.2V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Max clock frequency

freqop

500

MHz

Application Frequency Range

freqApp

233

MHz

Input clock duty cycle

dtin

CLK stabilization

TSTAB

µs

SPECIFICATION

Switching Characteristics (VDDQ2.5/1.8 = 2.5V +/- 0.2V ) (see note 1)

TA = 0 - 70°C; Supply Voltage AVDD = 2.5V+/-0.2V, VDDQ2.5/1.8 = 2.5 V +/- 0.2V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

Period jitter

Tjit (per)

Period jitter

-60

Half-period jitter

T(jit_hper)

Half period jitter

-75

Cycle to Cycle Jitter

Tcyc-Tcyc

Cycle to Cycle jitter

-60

Static Phase Offset

T(SPO)

-50

Output to Output Skew

Tskew

DDR(0:5)

Output Duty Cycle

tduty

Output clock slew rate

tsl(o)

Measured from 20% to 80% of

VDDQ

1.5

V/ns

1. Switching characteristics guaranteed for operating frequency range

SPECIFICATION

ICS9P936 数据表(PDF) 7 Page - Integrated Device Technology

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