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ATmega16 数据表(PDF) 208 Page - ATMEL Corporation |
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ATmega16 数据表(HTML) 208 Page - ATMEL Corporation |
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208 / 357 page  208 2466S–AVR–05/09 ATmega16(L) will require 25 ADC clocks. This is because the ADC must be disabled and re-enabled after every conversion. In Free Running mode, a new conversion will be started immediately after the conversion com- pletes, while ADSC remains high. For a summary of conversion times, see Table 81. Figure 101. ADC Timing Diagram, First Conversion (Single Conversion Mode) Figure 102. ADC Timing Diagram, Single Conversion MSB of Result LSB of Result ADC Clock ADSC Sample & Hold ADIF ADCH ADCL Cycle Number ADEN 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 First Conversion Next Conversion 3 MUX and REFS Update MUX and REFS Update Conversion Complete 1 2 3 4 5 6 7 8 9 10 11 12 13 MSB of Result LSB of Result ADC Clock ADSC ADIF ADCH ADCL Cycle Number 12 One Conversion Next Conversion 3 Sample & Hold MUX and REFS Update Conversion Complete MUX and REFS Update |
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