ATmega165 datasheet(52/336 Pages) ATMEL

52 / 336 page

ATmega165/V

2573G–AVR–07/09

External Interrupt Control

The External Interrupt Control Register A contains control bits for interrupt sense

control.

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the

corresponding interrupt mask are set. The level and edges on the external INT0 pin that

activate the interrupt are defined in Table 24. The value on the INT0 pin is sampled

before detecting edges. If edge or toggle interrupt is selected, pulses that last longer

than one clock period will generate an interrupt. Shorter pulses are not guaranteed to

generate an interrupt. If low level interrupt is selected, the low level must be held until

the completion of the currently executing instruction to generate an interrupt.

Bit

7654

321

–

ISC01

ISC00

EICRA

Read/Write

RRRR

R/W

Initial Value

0000

000

Table 24. Interrupt 0 Sense Control

ISC01

ISC00

Description

The low level of INT0 generates an interrupt request.

Any logical change on INT0 generates an interrupt request.

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

ATmega165 数据表(PDF) 52 Page - ATMEL Corporation