24

3677D–DFLASH–04/09

AT25DF021

11.1.5

WEL Bit

The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is

in the logical “0” state, the device will not accept any Byte/Page Program, erase, Protect Sector,

Unprotect Sector, Program OTP Security Register, or Write Status Register commands. The

WEL bit defaults to the logical “0” state after a device power-up or reset operation. In addition,

the WEL bit will be reset to the logical “0” state automatically under the following conditions:

• Write Disable operation completes successfully

• Write Status Register operation completes successfully or aborts

• Protect Sector operation completes successfully or aborts

• Unprotect Sector operation completes successfully or aborts

• Program OTP Security Register operation completes successfully or aborts

• Byte/Page Program operation completes successfully or aborts

• Block Erase operation completes successfully or aborts

• Chip Erase operation completes successfully or aborts

• Hold condition aborts

If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts

due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is

deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire

opcode for a Byte/Page Program, erase, Protect Sector, Unprotect Sector, Program OTP Secu-

rity Register, or Write Status Register command must have been clocked into the device.

11.1.6

RDY/BSY Bit

The RDY/BSY bit is used to determine whether or not an internal operation, such as a program

or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase

cycle, new Status Register data must be continually clocked out of the device until the state of

the RDY/BSY bit changes from a logical “1” to a logical “0”.

Figure 11-1. Read Status Register

SCK

CS

SI

SO

MSB

23

1

0

00000101

67

5

410 11

9

812

21 22

17

20

19

18

15 16

13 14

23 24

28 29

27

26

25

30

OPCODE

MSB

MSB

DDDDDD

DD

D

D

MSB

DDDDDD

D

D

D DD

D D D

ST

DATA

ATUS REGISTER

ST

DATA

ATUS REGISTER

ST

DATA

ATUS REGISTER

HIGH-IMPEDANCE