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R32C152 数据表(PDF) 97 Page - Renesas Technology Corp |
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R32C152 数据表(HTML) 97 Page - Renesas Technology Corp |
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97 / 133 page ![]() REJ03B0231-0102 Rev.1.02 Nov 30, 2009 Page 97 of 130 R32C/152 Group 5. Electrical Characteristics Note: 1. The device is operationally guaranteed under these operating conditions. Figure 5.1 Clock Cycle Time Table 5.5 Operating Conditions (4/6) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta =Topr, unless otherwise noted) (1) Symbol Characteristic Value Unit Min. Typ. Max. f(XIN) Main clock oscillator frequency 48 MHz f(XRef) Reference clock frequency 24 MHz f(PLL) PLL clock oscillator frequency 96 144 MHz f(Base) Base clock frequency 64 MHz tc(Base) Base clock cycle time 15.625 ns f(CPU) CPU operating frequency 64 MHz tc(CPU) CPU clock cycle time 15.625 ns f(BCLK) Peripheral bus clock operating frequency 32 MHz tc(BCLK) Peripheral bus clock cycle time 31.25 ns f(PER) Peripheral clock source frequency 32 MHz f(XCIN) Sub clock oscillator frequency 32.768 50 kHz Base clock (Internal signal) t c(Base) Peripheral bus clock (Internal signal) t c(BCLK) CPU clock (Internal signal) t c(CPU) |
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