AT68166HT datasheet(11/15 Pages) ATMEL

部件名	AT68166HT

功能描述	Rad Hard 16 MegaBit 3.3V 5V Tolerant SRAM Multi-Chip Module

PDF	15 Pages

Scroll/Zoom	100%

制造商	ATMEL [ATMEL Corporation]

网页	http://www.atmel.com

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11 / 15 page

7843A–AERO–10/09

AT68166HT

Read Cycle

Table 5. Read cycle timings(1)

Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.

2. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Wave-

forms” on page 9.)

Read Cycle 1.

Address Controlled (CS = OE = VIL, WE = VIH)

Read Cycle 2.

Chip Select Controlled (WE = VIH)

Symbol

Parameter

AT68166HT-25

AT68166HT-20

AT68166HT-18

(preliminary)

Unit

min

max

min

max

min

max

TAVAV

Read cycle time

TAVQV

Address access time

TAVQX

Address valid to low Z

TELQV

Chip-select access time

TELQX

CS low to low Z(2)

5-5-5-

TEHQZ

CS high to high Z(2)

-10-

TGLQV

Output Enable access time

TGLQX

OE low to low Z(2)

2-2-2-

TGHQZ

OE high to high Z (2)

-10-

ADDRESS

DOUT

CSx

DOUT

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