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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ATmega64A 数据表(PDF) 20 Page - ATMEL Corporation |
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ATmega64A 数据表(HTML) 20 Page - ATMEL Corporation |
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20 / 392 page  20 8160C–AVR–07/09 ATmega64A Figure 7-2. Data Memory Map 7.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk CPU cycles as described in Figure 7-3. Memory Configuration B 32 Registers 64 I/O Registers Internal SRAM (4000 x 8) $0000 - $001F $0020 - $005F $1000 $0FFF $FFFF $0060 Data Memory External SRAM (0 - 64K x 8) Memory Configuration A 32 Registers 64 I/O Registers Internal SRAM (4096 x 8) $0000 - $001F $0020 - $005F $1100 $10FF $FFFF $0060 - $00FF Data Memory External SRAM (0 - 64K x 8) 160 Ext I/O Reg. $0100 |
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