SC656

4

Applications Information (continued)

Output Open Circuit Protection

Over-Voltage Protection (OVP) at the OUT pin prevents

the charge pump from producing an excessively high

output voltage. In the event of an open circuit between

the OUT pin and all current sinks (no loads connected),

the charge pump runs in open loop and the voltage rises

up to the OVP limit. OVP operation is hysteretic, meaning

the charge pump will momentarily turn off until V

sufficiently reduced. The maximum OVP threshold is 6.0V,

allowing the use of a ceramic output capacitor rated

at 6.3V.

Over-Temperature Protection

The Over-Temperature (OT) protection circuit prevents the

device from overheating and experiencing a catastrophic

failure. When the junction temperature exceeds 65°C, the

device goes into thermal shutdown with all outputs dis-

abled until the junction temperature is reduced. All regis-

ter information is retained during thermal shutdown.

Hysteresis of 20°C is provided to ensure that the device

cools sufficiently before re-enabling.

Charge Pump Output Current Limit

The device limits the charge pump current at the OUT pin.

If the OUT pin is shorted to ground, or V

2.5V, the typical output current limit is 70mA. The output

current is limited to 225mA when over loaded resistively

with V

LED Float Detection

Float detect is a fault detection feature of the LED back-

light outputs. If an output is programmed to be enabled

and an open circuit fault occurs at any backlight output,

that output will be disabled to prevent a sustained output

OVP condition from occurring due to the resulting open

loop. Float detect ensures device protection but does not

ensure optimum performance.

PCB Layout Considerations

The layout diagram in Figure 2 illustrates a proper two

layer PCB layout for the SC656 and supporting compo-

nents. Following fundamental layout rules is critical for

achieving the performance specified in the Electrical

Characteristics table. The following guidelines are rec-

ommended when developing a PCB layout:

Figure 2 — Recommended Layout

COUT

ISETS

BL1

C2-

GND

BANK2

ENS

BL7

IN

OUT

SC656

ISETM

GND

RSETS

GND

IN

BANK1

RSETM

CIN

GND

Ground Plane

C1

C2