BQ20Z65DBT-R1 datasheet(8/23 Pages) TI

8 / 23 page

bq20z65-R1

SLUS990 – DECEMBER 2009

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

Over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,

V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V(TOUT)

Output voltage

I(TOUT) = 0 mA; TA = 25°C

V(REG25)

I(TOUT) = 1 mA; RDS(on) = (V(REG25) - V(TOUT) )/ 1 mA; TA =

RDS(on)

TOUT pass element resistance

100

Ω

–40°C to 100°C

LED OUTPUTS

VOL

Output low voltage

LED1, LED2, LED3, LED4, LED5

0.4

VCELL+ HIGH VOLTAGE TRANSLATION

VC(n) - VC(n+1) = 0 V;

0.950

0.975

TA = –40°C to 100°C

V(VCELL+OUT)

VC(n) - VC(n+1) = 4.5 V;

0.275

0.3

0.375

TA = –40°C to 100°C

internal AFE reference voltage ;

V(VCELL+REF)

Translation output

0.965

0.975

0.985

TA = –40°C to 100°C

V(VCELL+PACK

Voltage at PACK pin;

0.98 ×

1.02 ×

V(PACK)/18

)

TA = –40°C to 100°C

V(PACK)/18

Voltage at BAT pin;

0.98 ×

1.02 ×

V(VCELL+BAT)

V(BAT)/18

TA = –40°C to 100°C

V(BAT)/18

CMMR

Common mode rejection ratio

VCELL+

K= {VCELL+ output (VC5=0V; VC4=4.5V) - VCELL+

0.147

0.150

0.153

output (VC5=0V; VC4=0V)}/4.5

Cell scale factor

K= {VCELL+ output (VC2=13.5V; VC1=18V) - VCELL+

output

0.147

0.150

0.153

(VC5=13.5V; VC1=13.5V)}/4.5

Drive Current to VCELL+

VC(n) - VC(n+1) = 0V; VCELL+ = 0 V;

I(VCELL+OUT)

μA

capacitor

TA = –40°C to 100°C

CELL output (VC2 = VC1 = 18 V) - CELL output (VC2 =

V(VCELL+O)

CELL offset error

-18

-1

VC1 = 0 V)

IVCnL

VC(n) pin leakage current

VC1, VC2, VC3, VC4, VC5 = 3 V

-1

0.01

μA

CELL BALANCING

internal cell balancing FET

RDS(on) for internal FET switch at

RBAL

200

400

600

Ω

resistance

VDS = 2 V; TA = 25°C

HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA = 25°C (unless otherwise noted)

VOL = 25 mV (min)

OL detection threshold voltage

V(OL)

VOL = 100 mV; RSNS = 0, 1

100

110

accuracy

VOL = 205 mV (max)

185

205

225

V(SCC) = 50 mV (min)

SCC detection threshold voltage

V(SCC)

V(SCC) = 200 mV; RSNS = 0, 1

180

200

220

accuracy

V(SCC) = 475 mV (max)

428

475

523

V(SCD) = –50 mV (min)

–30

–50

–70

SCD detection threshold voltage

V(SCD)

V(SCD) = –200 mV; RSNS = 0, 1

–180

–200

–220

accuracy

V(SCD) = –475 mV (max)

–428

–475

–523

tda

Delay time accuracy

±15.25

μs

Protection circuit propagation

tpd

μs

delay

FET DRIVE CIRCUIT; TA = 25°C (unless otherwise noted)

V(DSGON) = V(DSG) - V(PACK);

V(DSGON)

DSG pin output on voltage

V(GS) connected to 10 MΩ; DSG and CHG on;

TA = –40°C to 100°C

V(CHGON) = V(CHG) - V(BAT);

V(CHGON)

CHG pin output on voltage

V(GS) = 10 MΩ; DSG and CHG on;

TA = –40°C to 100°C

V(DSGOFF)

DSG pin output off voltage

V(DSGOFF) = V(DSG) - V(PACK)

0.2

V(CHGOFF)

CHG pin output off voltage

V(CHGOFF) = V(CHG) - V(BAT)

0.2

V(CHG): V(PACK) ≥ V(PACK) + 4V

400

1000

Rise time

CL= 4700 pF

μs

V(DSG): V(BAT) ≥V(BAT) + 4V

400

1000

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