STi7108

Introduction

Doc ID 16790 Rev 1

3/12

1.1

STi7108 features summary

CPUs

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Applications CPU, ST40-300, dual-issue, MMU, 32KI, 32KD caches, 500 MHz

delivering >900DMIPs:

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Includes an L2 cache, 256KB, 2-way set associative

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Includes a tightly coupled vector FPU to accelerate 3D graphics transformations

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Real-time CPU for a/v real-time control and network processing offload - ST40-300,

dual-issue, MMU, 32KI, 32KD caches, 500 MHz delivering >900DMIPs

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Additional ST231 CPU available for further offloading of the applications CPU with

multimedia, security and networking tasks

2D Graphics acceleration

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Link list based, multi-operator 2D graphics blitter

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Supports rendering, formatting and pre-composition of 2D graphics and 3D-like user

interface effects

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Up to 266 Mpixels/sec with destination alpha blending

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Tile RAM memory bandwidth saver accelerates blitter based pre-composition of virtual

graphics planes before display

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Support for concurrent blitter use by applications and composition threads

3D Graphics acceleration

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True 3D graphics and 2D vector graphics acceleration engine (GPU), optimized for

consumer applications

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Programmable Vertex (Geometry) processor and Fragment (Pixel) processor:

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Accelerated four times full scene anti-aliasing (4×FSAA)

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Tile based for memory bandwidth efficiency

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Supports decoded video as textures

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Compatible with industry standard APIs, OpenGL ES 1.1/2.0 and Open VG 1.0/1.1

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Rendering performance up to either 720p60 with 4×FSAA or 1080i60 with 4×FSAA

(without lighting) with simple pixel shaders, and up to 720p30 with 4×FSAA with

complex pixel shaders (with lighting)