ADL5802

Rev. 0 | Page 6 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

1

GND

2

GND

3

OP1+

4

OP1–

5

GND

6

VPOS

NOTES

1. THERE IS AN EXPOSED PADDLE THAT

MUST BE SOLDERED TO GROUND.

15 OP2–

16 OP2+

17 GND

18 GND

14 GND

13 VPOS

ADL5802

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Function

1, 2, 5, 8, 11,

14, 17, 18, 21

GND

Device Common (DC Ground).

3, 4

OP1+, OP1−

Channel 1 Mixer Differential Output Terminals. Bias must be applied through pull-up choke inductors or

the center tap of the IF transformer.

6, 13, 24

VPOS

Positive Supply Voltage. 5.0 V nominal.

7

ENBL

Device Enable. Pull low or leave disconnected to enable the device; pull high to disable the device.

9, 10

LOIP, LOIN

Differential LO Input Terminals. Internally matched to 50 Ω; must be ac-coupled.

12

VSET

High Input IP3 Bias Control. For high input IP3 performance, apply ~4 V to 5 V. Improved noise figure (NF)

performance and lower supply current can be set by applying ~2 V to 3 V to the VSET pin. A resistor can be

connected to the supply to raise the voltage, whereas a resistor to GND lowers the voltage.

15, 16

OP2−, OP2+

Channel 2 Mixer Differential Output Terminals. Bias must be applied through pull-up choke inductors or

the center tap of the IF transformer.

19, 20

RF2−, RF2+

Differential RF Input Terminals for Channel 2. Internally matched to 50 Ω; must be ac-coupled.

22, 23

RF1−, RF1+

Differential RF Input Terminals for Channel 1. Internally matched to 50 Ω; must be ac-coupled.

EPAD

Exposed Paddle. Must be soldered to ground.