PEX 8664, PCI Express Gen 2 Switch, 64 Lanes, 16 Ports

© PLX Technology, www.plxtech.com

Page 4 of 4

5/14/2009, Version 1.1

server design where, in a quad or multi processor

system, users can assign endpoints/slots to CPU cores to

distribute the system load. The packets directed to

different CPU cores will go to different (user assigned)

PEX 8664 upstream ports, allowing better queuing and

load balancing capability for higher performance.

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

x8

x4s

Memory

Memory

Memory

Memory

x8s

x4

x16

Endpoint

Endpoint

Endpoint

Endpoint

Endpoint

Endpoint

Endpoint

Endpoint

PCIe Gen1 or PCIe Gen2 slots

x8

PEX 8664

PEX 8664

PEX 8664

PEX 8664

Chipset

Chipset

Chipset

Chipset

Figure 6. Host Centric Dual Upstream

Embedded or Communications Systems

The PEX 8664’s 64 lanes can come in handy for

embedded or communications applications requiring

heavy processing and/or connectivity to multiple

endpoints. Figure 7a shows an embedded system where

the PEX 8664 is being used to fan-out to eight endpoints

using x8 and x16 links. Figure 7b shows a

communications system where the PEX 8664 is using

x16 downstream links to fan out to three CPUs which

have been configured as endpoints. These CPUs will run

as endpoints, conducting different processing tasks while

the host CPU (connected to the PEX 8664 via a x16

upstream link) manages them.

Chip

Set

Chip

Set

CPU

CPU

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

PEX 8664

PEX 8664

x16

x16s

Figure 7b. Comms System

Chip

Set

Chip

Set

CPU

CPU

x16

x8s

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

PEX 8664

PEX 8664

Figure 7a. Embedded System

Chip

Set

Chip

Set

CPU

CPU

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

PEX 8664

PEX 8664

x16

x16s

Figure 7b. Comms System

Chip

Set

Chip

Set

CPU

CPU

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

PEX 8664

PEX 8664

x16

x16s

Chip

Set

Chip

Set

CPU

CPU

CPU

CPU

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

PEX 8664

PEX 8664

PEX 8664

PEX 8664

x16

x16s

Figure 7b. Comms System

Chip

Set

Chip

Set

CPU

CPU

x16

x8s

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

PEX 8664

PEX 8664

Figure 7a. Embedded System

Chip

Set

Chip

Set

CPU

CPU

x16

x8s

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

PEX 8664

PEX 8664

Chip

Set

Chip

Set

CPU

CPU

CPU

CPU

x16

x8s

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

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I/O

PEX 8664

PEX 8664

PEX 8664

PEX 8664

Figure 7a. Embedded System

Host Failover

The PEX 8664 can also be utilized in applications where

host failover is required. In the application shown in

Figure 8, two hosts may be active simultaneously and

controlling their own domains while exchange status

information through doorbell registers or I

The devices can be programmed to trigger fail-over if

the heartbeat information is not provided. In the event of

a failure, the surviving device will reset the endpoints

connected to the failing CPU and enumerate them in its

own domain without impacting the operation of

endpoints already in its domain.

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

x8

x4 & x8

Chipset

Chipset

Chipset

Chipset

PEX 8664

PEX 8664

PEX 8664

PEX 8664

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

x8

Chipset

Chipset

Chipset

Chipset

PEX 8664

PEX 8664

PEX 8664

PEX 8664

x8s

Figure 8. Host Fail-Over

N+1 Fail-Over in Storage Systems

The PEX 8664’s Multi-Host feature can also be used to

develop storage array clusters where each host manages

a set of storage devices independent of others. Users can

designate one of the hosts as the failover-host for all the

other hosts while actively managing its own endpoints.

The failover-host will communicate with other hosts for

status/heartbeat information and execute a failover event

if/when it gets triggered (see Figure 9).

x4

x4

x8

x8

x4

x8

x8

x4

CPU

CPU

PEX 8664

PEX 8664

PEX 8664

PEX 8664

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8612

PEX 8612

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8612

PEX 8612

PEX 8612

PEX 8612

CPU

CPU

CPU

CPU

CPU

CPU

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8612

PEX 8612

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8612

PEX 8612

PEX 8612

PEX 8612

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8616

PEX 8616

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8616

PEX 8616

PEX 8616

PEX 8616

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8616

PEX 8616

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8616

PEX 8616

PEX 8616

PEX 8616

Figure 9. N+1 Failover