PEX 8680, PCI Express Gen 2 Switch, 80 Lanes, 20 Ports

© PLX Technology, www.plxtech.com

Page 4 of 4

5/14/2009, Version 1.1

Applications

Suitable for host-centric as well as peer-to-peer traffic

patterns, the PEX 8680 can be configured for a wide

variety of form factors and applications.

Host Centric Fan-out

The PEX 8680, with its symmetric or asymmetric lane

configuration capability, allows user-specific tuning to a

variety of host-centric applications. Figure 6 shows a

server design where, in a quad or multi processor

system, users can assign endpoints/slots to CPU cores to

distribute the system load. The packets directed to

different CPUs will go to different (user assigned) PEX

8680 upstream ports, allowing better queuing and load

balancing capability for higher performance.

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

x8

x4s

Memory

Memory

Memory

Memory

x8s

x4

x16

Endpoint

Endpoint

Endpoint

Endpoint

Endpoint

Endpoint

Endpoint

Endpoint

PCIe Gen1 or PCIe Gen2 slots

x8

PEX 8680

PEX 8680

PEX 8680

PEX 8680

Chipset

Chipset

Chipset

Chipset

Figure 6. Host Centric Dual Upstream

Multi-Host Systems

In multi-host mode, the PEX 8680 can support up to six

hosts at once. By creating six virtual switches, the PEX

8680 allows six hosts to fan-out to their respective

endpoints. This reduces the number of switches required

for fan-out, saving precious board space and power. In

Figure 7, the PEX 8680 is being shared by six different

CPU cores (hosts) on three servers, with each CPU core

running its own applications (I/Os). The PEX 8680

assigns the endpoints to the appropriate host and isolates

them from the other hosts. In Figure 7, the endpoints are

assigned to the CPU core of the same color.

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Chip

Set

Chip

Set

Chip

Set

Chip

Set

Chip

Set

Chip

Set

PEX 8680

PEX 8680

Figure 7. Multi-Host System

Embedded or Communications Systems

The PEX 8680’s 80 lanes can come in handy for

embedded or communications applications requiring

heavy processing and/or connectivity to multiple

endpoints. Figure 8a shows an embedded system where

the PEX 8680 is being used to fan-out to eight endpoints

using x8 and x16 links. Figure 8b shows a

communications system where the PEX 8680 is using

x16 and x8 links to fan out to I/Os and three CPUs

which have been configured as endpoints. These CPUs

will run as endpoints, conducting different processing

tasks while the host CPU (connected to the PEX 8680

via a x16 upstream link) manages them.

x16s

x8s

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Chip

Set

Chip

Set

CPU

CPU

CPU

CPU

x16

Figure 8b. Comms System

Chip

Set

Chip

Set

CPU

CPU

CPU

CPU

x16

x16s

& x8s

PEX 8680

PEX 8680

PEX 8680

PEX 8680

Figure 8a. Embedded System

I/O

I/O

I/O

I/O

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

CPU

Endpoint

I/O

I/O

I/O

I/O

PEX 8680

PEX 8680

PEX 8680

PEX 8680

N+1 Fail-Over in Storage Systems

The PEX 8680’s Multi-Host feature can also be used to

develop storage array clusters where each host manages

a set of storage devices independent of others (Figure 9).

Users can designate one of the hosts as the failover-host

for all the other hosts while actively managing its own

endpoints. The failover-host will communicate with

other hosts for status/heartbeat information and execute a

failover event if/when it gets triggered.

x4

x4

x8

x8

x4

x8

x8

x4

CPU

CPU

PEX 8680

PEX 8680

PEX 8680

PEX 8680

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8612

PEX 8612

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8612

PEX 8612

PEX 8612

PEX 8612

CPU

CPU

CPU

CPU

CPU

CPU

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8612

PEX 8612

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8612

PEX 8612

PEX 8612

PEX 8612

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8616

PEX 8616

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8616

PEX 8616

PEX 8616

PEX 8616

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8616

PEX 8616

8 Disk Chassis

FC

FC

x4

x4

FC

FC

PEX 8616

PEX 8616

PEX 8616

PEX 8616

Figure 9. N+1 Failover