MPC5604P datasheet(49/84 Pages) FREESCALE

49 / 84 page

MPC5604P Microcontroller Data Sheet, Rev. 5

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

3.11

FMPLL electrical characteristics

Table 27. PLLMRFM electrical specifications1

(VDDPLL = 3.0 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH)

1 All values given are initial design targets and subject to change.

Symbol

Parameter

Conditions

Value

Unit

min

max

fref_crystal

fref_ext

PLL reference frequency range2

2 Considering operation with PLL not bypassed.

Crystal reference

MHz

fpll_in

Phase detector input frequency range

(after pre-divider)

—4

MHz

fFMPLLO

Clock frequency range in normal

mode

—

120

MHz

fFREE

Free running frequency

Measured using

clock division —

typically /16

150

MHz

fsys

On-chip PLL frequency2

—

120

MHz

tCYC

System clock period

—

1 / fsys

fLORL

fLORH

Loss of reference frequency window3

3 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked

mode.

Lower limit

1.6

3.7

MHz

Upper limit

fSCM

Self-clocked mode frequency4,5

4 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside

the fLOR window.

—

150

MHz

CJITTER

TCLKOUT

period

jitter6,7,8,9

Short-term jitter10

fSYS maximum

-4

% fCLKOUT

Long-term jitter (avg.

over 2 ms interval)

fPLLIN = 16 MHz

(resonator)

fPLLCLK @ 64

MHz, 4000

cycles

—10

tlpll

PLL lock time 11, 12

—

200

μs

tdc

Duty cycle of reference

—40

fLCK

Frequency LOCK range

—

-6

% fsys

fUL

Frequency un-LOCK range

—

-18

% fsys

fCS

fDS

Modulation Depth

Center spread

±0.25

±4.013

%fsys

Down Spread

-0.5

-8.0

fMOD

Modulation frequency14

—

kHz

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