HT66F40 datasheet(39/224 Pages) HOLTEK

39 / 224 page

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60

Rev. 1.00

November 3, 2009

Control Register

A single register, SMOD, is used for overall control of the internal clocks within the device.

· SMOD Register

Bit

76543210

Name

CKS2

CKS1

CKS0

FSTEN

LTO

HTO

IDLEN

HLCLK

R/W

POR

00000011

Bit 7~5

CKS2~CKS0: The system clock selection when HLCLK is

²0²

000: fL (fLXT or fLIRC)

001: fL (fLXT or fLIRC)

010: fH/64

011: fH/32

100: fH/16

101: fH/8

110: fH/4

111: fH/2

These three bits are used to select which clock is used as the system clock source. In addition

to the system clock source, which can be either the LXT or LIRC, a divided version of the high

speed system oscillator can also be chosen as the system clock source.

Bit 4

FSTEN: Fast Wake-up Control (only for HXT)

0: Disable

1: Enable

This is the Fast Wake-up Control bit which determines if the fSUB clock source is initially used

after the device wakes up. When the bit is high, the fSUB clock source can be used as a

temporary system clock to provide a faster wake up time as the fSUB clock is available.

Bit 3

LTO: Low speed system oscillator ready flag

0: Not ready

1: Ready

This is the low speed system oscillator ready flag which indicates when the low speed system

oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in

the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after

1024 clock cycles if the LXT oscillator is used and 1~2 clock cycles if the LIRC oscillator is used.

Bit 2

HTO: High speed system oscillator ready flag

0: Not ready

1: Ready

This is the high speed system oscillator ready flag which indicates when the high speed system

oscillator is stable. This flag is cleared to

²0² by hardware when the device is powered on and

then changes to a high level after the high speed system oscillator is stable. Therefore this flag

will always be read as

²1² by the application program after device power-on. The flag will be

low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to

a high level after 1024 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if

the ERC or HIRC oscillator is used.

Bit 1

IDLEN: IDLE Mode control

0: Disable

1: Enable

This is the IDLE Mode Control bit and determines what happens when the HALT instruction is

executed. If this bit is high, when a HALT instruction is executed the device will enter the

IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to

keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU

and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the

SLEEP Mode when a HALT instruction is executed.

Bit 0

HLCLK: system clock selection

0: fH/2~fH/64 or fL

1: fH

This bit is used to select if the fH clock or the fH/2~fH/64 or fL clock is used as the system

clock. When the bit is high the fH clock will be selected and if low the fH/2~fH/64 or fL clock will

be selected. When system clock switches from the fH clock to the fL clock and the fH clock will

be automatically switched off to conserve power.

HT66F40 数据表(PDF) 39 Page - Holtek Semiconductor Inc

HT66F40 数据表(HTML) 39 Page - Holtek Semiconductor Inc

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