HT82A620R datasheet(21/72 Pages) HOLTEK

21 / 72 page

HT82A520R/HT82A620R

Rev.1.00

October 23, 2009

When the Timer/Event Counter is read or if data is written

to the preload registers, the clock is inhibited to avoid er-

rors, however as this may result in a counting error, this

should be taken into account by the programmer. Care

must be taken to ensure that the timers are properly in-

itialised before using them for the first time. The associ-

ated timer interrupt enable bits in the interrupt control

rupt associated with the timer will remain inactive. The

edge select, timer mode and clock source control bits in

timer control register must also be correctly set to ensure

the timer is properly configured for the required applica-

tion. It is also important to ensure that an initial value is

first loaded into the timer register before the timer is

switched on; this is because after power-on the initial

value of the timer register is unknown. After the timer has

been initialised the timer can be turned on and off by con-

trolling the enable bit in the timer control register. Note

that setting the timer enable bit high to turn the timer on,

should only be executed after the timer mode bits have

been properly setup. Setting the timer enable bit high to-

gether with a mode bit modification, may lead to improper

timer operation if executed as a single timer control regis-

ter byte write instruction.

When the Timer/Event counter overflows, its corre-

sponding interrupt request flag in the interrupt control

will in turn generate an interrupt signal. However irre-

spective of whether the timer interrupt is enabled or not,

a Timer/Event counter overflow will also generate a

wake-up signal if the device is in a Power-down condi-

tion. This situation may occur if the Timer/Event Counter

is in the Event Counting Mode and if the external signal

continues to change state. In such a case, the

Timer/Event Counter will continue to count these exter-

nal events and if an overflow occurs the device will be

woken up from its Power-down condition. To prevent

such a wake-up from occurring, the timer interrupt re-

quest flag should first be set high before issuing the

HALT instruction to enter the Power Down Mode.

Timer Program Example

This program example shows how the Timer/Event

Counter registers are setup, along with how the inter-

rupts are enabled and managed. Note how the

Timer/Event Counter is turned on, by setting bit 4 of the

Timer Control Register. The Timer/Event Counter can

be turned off in a similar way by clearing the same bit.

This example program sets the Timer/Event Counter

tobe in the timer mode, which uses the internal system

clock as the clock source.

org 04h

; USB interrupt vector

reti

org 08h

; external interrupt vector

reti

org 0ch

; Timer/Event Counter interrupt vector

jmp tmr0int

; jump here when Timer/Event Counter overflows

org 010h

; SPI interrupt vector

reti

org 20h

; main program

;internal Timer/Event Counter interrupt routine

tmrint:

; Timer/Event Counter main program placed here

reti

begin:

;setup Timer/Event Counter registers

mov a,0e8h

; setup low byte preload value for Timer/Event Counter

mov tmrl,a

; low byte must be setup before high byte

mov a,09bh

; setup high byte preload value for Timer/Event Counter

mov tmrh,a

;

mov a,080h

; setup Timer control register TMRC

mov tmrc,a

; Timer/Event Counter clock source is fSYS/4

; setup interrupt register

mov a,009h

; enable master interrupt and timer interrupts

mov intc0,a

set tmrc.4

; start Timer/Event Counter _ note mode bits must be previously setup

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