MPC8535EBVTATH datasheet(120/126 Pages) FREESCALE

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MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Guidelines for High-Speed Interface Termination

Freescale Semiconductor

120

The following pins must be connected to XGND if not used:

•

SD1_RX[7:4]

•

SD1_RX[7:4]

•

SD1_REF_CLK

•

SD1_REF_CLK

3.11.3

SerDes 2 Interface Entirely Unused

If the high-speed SerDes 2 interface (SGMII/ SATA) is not used at all, the unused pin should be terminated as described in this

section. There are several Reserved pins that need to be either left floating or connected to X2GND. See SerDes2 in

Table 1Table 1 for details.

The following pins must be left unconnected (float):

•

SD2_TX[0]

•

SD2_TX[0]

•

Reserved pins L8, L9

The following pins must be connected to X2GND:

•

SD2_RX[0]

•

SD2_RX[0]

•

SD2_REF_CLK

•

SD2_REF_CLK

The POR configuration pin cfg_srds2_prtcl[0:2] on TSEC1_TXD[2], TSEC3_TXD[2], TSEC_1588_PUSLE_OUT1 can be

used to power down SerDes 2 block for power saving. Note that both S2VDD and X2VDD must remain powered.

Ordering Information

Ordering information for the parts fully covered by this specification document is provided in Section 4.1, “Part Numbers Fully

Addressed by This Document.”

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