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MPC8535ECVTATH 数据表(PDF) 42 Page - Freescale Semiconductor, Inc |
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MPC8535ECVTATH 数据表(HTML) 42 Page - Freescale Semiconductor, Inc |
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42 / 126 page  MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Freescale Semiconductor 42 Timing diagrams for FIFO appear in Figure 14 and Figure 15. . Figure 14. FIFO Transmit AC Timing Diagram Rise time TX_CLK (20%–80%) tFITR — — 0.75 ns Fall time TX_CLK (80%–20%) tFITF — — 0.75 ns GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time tFITDX 1 0.5 — 3.0 ns Note: 1. Data valid tFITDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time – Max Hold) 2. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency of the speed bins the part belongs to as well as the FIFO mode under operation. See Section 2.4.6, “Platform to FIFO Restrictions,” for more detailed description. Table 27. FIFO Mode Receive AC Timing Specification Parameter/Condition Symbol Min Typ Max Unit RX_CLK clock period1 tFIR 6.0 8.0 100 ns RX_CLK duty cycle tFIRH/tFIRH 45 50 55 % RX_CLK peak-to-peak jitter tFIRJ —— 250 ps Rise time RX_CLK (20%–80%) tFIRR — — 0.75 ns Fall time RX_CLK (80%–20%) tFIRF — — 0.75 ns RXD[7:0], RX_DV, RX_ER setup time to RX_CLK tFIRDV 1.5 ——ns RXD[7:0], RX_DV, RX_ER hold time to RX_CLK tFIRDX 0.5 ——ns Note: 1. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency of the speed bins the part belongs to as well as the FIFO mode under operation. See Section 2.4.6, “Platform to FIFO Restrictions,” for more detailed description. Table 26. FIFO Mode Transmit AC Timing Specification (continued) Parameter/Condition Symbol Min Typ Max Unit tFIT tFITH tFITF tFITDX TXD[7:0] TX_EN GTX_CLK TX_ER tFITDV tFITR |
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