MPC8544EBVTARF datasheet(28/120 Pages) FREESCALE

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MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC), MII Management

Figure 8. SGMII Transmitter DC Measurement Circuit

8.4

SGMII AC Timing Specifications

This section describes the SGMII transmit and receive AC timing specifications. Transmitter and receiver

characteristics are measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) or at the receiver

inputs (SD2_RX[n] and SD2_RX[n]) as depicted in Figure 10, respectively.

Table 25. DC Receiver Electrical Characteristics

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Supply Voltage

VDD_SRDS2

0.9

1.0

1.05

—

DC input voltage range

—

Input differential voltage

LSTS = 0

Vrx_diffpp

100

—

1200

2, 4

LSTS = 1

175

—

Loss of signal threshold

LSTS = 0

Vlos

—

100

3, 4

LSTS = 1

—

175

Input AC common mode voltage

Vcm_acpp

——

100

Receiver differential input impedance

Zrx_diff

—

120

—

Receiver common mode input impedance

Zrx_cm

—

Common mode input voltage

Vcm

xcorevss

—

xcorevss

Notes:

1. Input must be externally AC-coupled.

2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage

3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. Refer to

Section 17.4.3, “Differential Receiver (RX) Input Specifications,” for further explanation.

4. The LSTS shown in this table refers to the LSTSCD bit field of MPC8544E SerDes 2 control register 1.

5. VCM_ACp-p is also referred to as peak-to-peak AC common mode voltage.

6. On-chip termination to SGND_SRDS2 (xcorevss).

Transmitter

SD2_TX

Vos

VOD

MPC8544E SGMII

SerDes Interface

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